A reconfigurable accelerator for neuromorphic object recognition

Sabarad, J.; Kestur, Srinidhi; Park, Mi Sun; Dantara, Dharav; Narayanan, Vijaykrishnan; Chen, Yang; Khosla, Deepak

doi:10.1109/aspdac.2012.6165067

Cited by 22 publications

(26 citation statements)

References 10 publications

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“…This approach has been leveraged for software-defined radio applications (see for example Ramacher et al [37], CEA MAGALI [9,23] and StepNP [31]), in high-performance computing (for example by Maxeler [33]) and in the embedded vision domain (for example Vortex [29,40] for biologically-inspired vision acceleration, and NeuFlow [19] and nn-X [20], which focus on Convolutional Neural Network acceleration). Loose coupling of processors and accelerators through messagepassing channels is extremely scalable and power-efficient, as accelerators completely bypass the Von Neumann bottleneck, working only when they are fed with input.…”

Section: Related Workmentioning

confidence: 98%

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Conti

Marongiu

Pilkington

et al. 2015

J Sign Process Syst

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The end of Dennardian scaling in advanced technologies brought about new architectural templates to overcome the so-called utilization wall and provide Moore's Law-like performance and energy scaling in embedded SoCs. One of the most promising templates, architectural heterogeneity, is hindered by high cost due to the design space explosion and the lack of effective exploration tools. Our work provides three contributions towards a scalable and effective methodology for design space exploration in embedded MC-SoCs. First, we present the He-P2012 architecture, augmenting the state-of-art STMicroelectronics P2012 platform with heterogeneous shared-L1 coprocessors called HW processing elements (HWPE). Second, we propose a novel methodology for the semi-automatic definition and instantiation of shared-memory HWPEs from a C source, supporting both simple and structured data types. Third, we demonstrate that the integration of HWPEs can provide significant performance and energy efficiency benefits on a set of benchmarks originally developed for the homogeneous P2012, achieving up to 123x speedup on the accelerated code region (∼98 % of Amdahl's law limit) while saving 2/3 of the energy.

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Section: Related Workmentioning

confidence: 98%

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Conti

Marongiu

Pilkington

et al. 2015

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

“…1) Processing Elements Either a preexisting processing elements (PE) like DSP blocks [3] or general purpose processors can be found in today's SoCs. If the PEs are preexisting functions, there is no hardware reconfiguring ability in cores of an application to another.…”

Section: Proposed Noc Architecturementioning

confidence: 99%

“…In order to map functions in the task graph to physical cores in NoC, we used back-bone idea of NMAP [3] algorithm with some justification to fit into our architecture. Like NMAP algorithm, the aim is to place a vertex of graph near enough to each other in order to less communication cost and bandwidth decreasing.…”

Section: Core Mappingmentioning

confidence: 99%

“…Application specific design provides the minimum latency and power for running an application by customizing the design to optimally fit the application; hence we choose to use it, instead of general processing units. On the other hand, these configurable elements can be used to map customized accelerating hardwares, as suggested in [2,3], or approximated processing units, as shown in [4], for a specific use which results in reduction in application runtime. Another benefit of this re-configurability, is the displacement for core mapping.…”

Section: Introductionmentioning

confidence: 99%

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Application-specific power-aware mapping for reconfigurable NoC architectures

Goli

Ghasemazar

Navabi

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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In this paper, we propose a new topology-core reconfigurable architecture for network-on-chips (NoC). The majority of existing research on reconfigurable architectures is focused on either reconfiguring topology of NoC or reconfiguring processing elements of the network. Our approach uses a hybrid algorithm to take advantages of both these methods by using field programmable gate array (FPGA) as reconfigurable processing elements. Moreover, programmable switches among routers are applied for topology reconfigurability. The experimental results show extensive improvement over the state-of-the-art research in terms of power consumption, network performance and application execution time.

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“…The Table III represents the speedups in execution time gained by our pipeline architecture and two existing HMAX accelerators implementations for 256 × 256 grayscale images [10] [18]. The initial design of the HMAX accelerator [10] takes about 21.81ms per image with a frame rate of 45.85 fps, whereas the second design [18] takes about 11.04ms per image with a frame rate of 90.57f ps. Our multi-processor architecture gave an overall speedups of 3.14X and 1.52X over the initial design and the second design, although it is mapped to a single FPGA only.…”

Section: Timing Performancementioning

confidence: 99%

A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture

Chenini¹

2017

ijacsa

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Abstract-This paper presents an object recognition approach of outdoor autonomous systems identifying the nature of the interested object when observing an image. Therefore, seeking for effective and robust recognition method, the proposed approach is performed using a novel saliency based feature detector/descriptor which is combined with an object classifier to identify the nature of objects in an indoor or an outdoor environment. As known, bottom-up visual attention computational models need a considerable computational power and communication cost. A major challenge in this work is to deal with such image processing applications managing a large amount of the information processing and to work within real-time requirements by improving the processing speed.Based on interesting approach designing specific architectures for parallelism, this paper presents a solution for rapid prototyping of saliency-based object recognition applications. In order to meet computation and communication requirement, the developed pipelined architectures are composed of identical processing modules which can work concurrently with distributed memories and compute in parallel several sequential tasks with a high computational cost. We present hardware implementations with performance results on an Xilinx System-on-Programmable Chip (SoPC) target. The experimental results including execution times and application speedups as well as requirements in terms of computing resources show that the proposed homogeneous network of processors is efficient for embedding the proposed image processing application.

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A reconfigurable accelerator for neuromorphic object recognition

Cited by 22 publications

References 10 publications

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Application-specific power-aware mapping for reconfigurable NoC architectures

A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture

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