SEU induced errors observed in microprocessor systems

Asenek, V.; Underwood, Craig; Velazco, Raoul; Rezgui, S.; Oldfield, M.K.; Cheynet, P.; Ecoffet, R.

doi:10.1109/23.736542

Cited by 31 publications

(11 citation statements)

References 4 publications

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“…The second step is to determine the probability that a SEU cause a system error. It has been shown [10][11][12][13][14] that this probability is related with the application cross section, denoted by AP . To increase system reliability, the application cross section should be reduced by means of fault tolerant techniques.…”

Section: Introductionmentioning

confidence: 99%

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications

Brac¹,

Ferreyra²,

Velazco³

et al. 2009

2009 10th Latin American Test Workshop

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ISBN 978-1-4244-4207-2International audienceThis work presents a Fault Tolerant FPGA based Active Antenna system intended to be used in the space environment. The proposed design can control the electromagnetic radiation pattern emitted by an antenna array in real time with high reliability levels. The FPGA is a Commercial of the Shelf (COTS) device based on the Anti fuse technology. The design is optimized to reduce the area overhead allowing the control of multiple antennas by means of a single FPGA. The Fault Tolerance and high reliability achieved with the design is shown by means of a new test methodology

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Section: Introductionmentioning

confidence: 99%

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications

Brac¹,

Ferreyra²,

Velazco³

et al. 2009

2009 10th Latin American Test Workshop

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“…Reference [5] explored a method, based on the use of a commercially available microprocessor software simulator, for the prediction of upset errors in microprocessor systems. An actual satellite application built on an 80C51 micro-controller was simulated concurrently with the injection of upsets in microcontroller registers.…”

Section: Introductionmentioning

confidence: 99%

Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

Velazco

Rezgui

Ecoffet

2000

IEEE Trans. Nucl. Sci.

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115

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--This paper investigates an approach to study the effects of upsets on the operation of microprocessorbased digital architectures. The method is based on the injection of bitf lips, randomly in time and location by using the capabilities of typical application boards. Experimental results, obtained on programs running on two different digital boards, built around an 80C51 microcontroller and a 320C50 Digital Signal Processor, illustrate the potentialities of this new strategy.

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“…The first approach focuses on breaking the device into functional blocks (e.g., register file, ALU), and determining the cross-sections and duty cycles of these blocks through testing and analysis. The duty cycle and cross-sections are then multiplied to determine the overall device cross-section [18]- [20]. The second approach focuses on simulations using hardware-description languages, such as VHDL.…”

Section: F Seu Propagation Modelingmentioning

confidence: 99%