Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

Velazco, Raoul; Rezgui, S.; Ecoffet, R.

doi:10.1109/23.903784

Cited by 115 publications

(33 citation statements)

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“…Aunque, el tiempo necesario para inyectar el fallo es relativamente corto, estos métodos son muy intrusivos ya que requieren la modificación del código original. En [15] Velazco et al describen una técnica software basada en rutinas de interrupción de servicio denominada CEU (Code Emulated Upset) para inyección de fallos. La implementación del método se realiza sobre una arquitectura hardware, denominada THESIC (Testbed for Harsh Environment Studies on Integrated Circuits), es una plataforma genérica que se encarga de generar las interrupciones que activan la inyección, las localizaciones del fallo, y de leer los resultados.…”

Section: Trabajos Previosunclassified

Dependability evaluation of COTS microprocessors via on-chip debugging facilities

Isaza-Gonzalez

Serrano-Cases

Restrepo-Calle

et al. 2016

2016 17th Latin-American Test Symposium (LATS)

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Resumen-Este artículo presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de Single-Event-Upsets (SEUs) en microprocesadores Commercial-off-the-shelf (COTS). Este método utiliza las ventajas que ofrecen las infraestructuras de depuración de los microprocesadores actuales, además del depurador estándar de GNU (GDB) para la ejecución y depuración de los programas de pruebas. Los experimentos desarrollados sobre microprocesadores reales, así como en las máquinas virtuales, demuestran la viabilidad y la flexibilidad de la propuesta como una solución de bajo costo para evaluar la fiabilidad de los microprocesadores COTS. Palabras claves-Commercial-off-the-shelf (COTS), depuración integrada en el chip, efectos de la radiación, fiabilidad de microprocesadores, inyección de fallos, errores lógicos. Abstract-This paper presents a fault injection tool and methodology for performing Single-Event-Upsets (SEUs) injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. This method takes advantage of the debug facilities of modern

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Section: Trabajos Previosunclassified

Dependability evaluation of COTS microprocessors via on-chip debugging facilities

Isaza-Gonzalez

Serrano-Cases

Restrepo-Calle

et al. 2016

2016 17th Latin-American Test Symposium (LATS)

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“…In [3] we proposed an initial estimation of τ obtained by using two fault injection methods that considered as targets of injection all the Special Function Registers of the microcontroller and the 128 bytes internal memory registers. The first considered method injects faults by executing suitable pieces of code and is called CEU (Code Emulating an Upset) technique [5] [6] the second method instead uses an HDL model of the device [7], for which code modifications are implemented in order to virtually change run-time every part composing the device. The two models were in accordance ( Table 1) and showed that the sensitivity to bit flips resulted strongly related to the executed program.…”

Section: Seu Effects On Program Execution Flowmentioning

confidence: 99%

Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers

Ottavi

Pontarelli

Leandri

et al. 2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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“…Las primeras aproximaciones se presentan en [Velazco et al 1990y Martinet 1992. El láser se utiliza para cortar pistas internas y conexiones metalizadas de los circuitos integrados, generando fallos permanentes.…”

Section: Inyección Mediante Radiación Láserunclassified

Validación de la arquitectura TTA mediante inyección física de fallos a nivel de PIN.

Clavero¹

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Cuando entre la sabiduría en tu corazón y la ciencia sea dulce para tu alma velará sobre ti la reflexión y te guardará la prudencia Proverbio A los míos, gracias de todo corazón Agradecimientos:Al Doctor D. Pedro Joaquín Gil Vicente, director de esta tesis, por su orientación y su constante ayuda.A los directores y promotores del proyecto Fault Injection for TTA, el Doctor Herbert Grünbacher, del Instituto Técnico de Carinthia, y el Doctor Herman Kopetz, de la Universidad Técnica de Viena, y en general, a todos los miembros del proyecto.A todos los compañeros del Departamento de Informática de Sistemas y Computadores (D.I.S.C.A.), y en especial a los integrantes del Grupo de Sistemas Tolerantes a Fallos al cual pertenezco.A mi familia, porque sin ellos no hubiera podido llegar hasta aquí. A mi marido, Eduardo, por su apoyo incondicional y su eterna paciencia.A todos, gracias. AbstractDependability has so far been used as a required characteristic in order to evaluate complex or critical systems, especially those in which a failure means a risk for human life or high economical losses. Nowadays, the development of embedded systems has increased in all areas, from industrial environments to household uses. Due to the commercial expansion of embedded systems and market competitiveness, many system designers take dependability into account. Dependability evaluation and system validation has to be carried out before the functional-live phase of the product. Since an "in situ" work may require a long time because of the low failure rate of components in modern circuits, it is useful to resort to a experimental validation that generates faulty events forcing the system to deal with them according to design specifications. Fault Injection is an experimental validation method with increasing acceptance based on the realization of controlled experiments where the observation of the system behaviour in present of faults is explicitly induced by the deliberate introduction (injection) of faults into the system.The effect of physical faults on current semiconductors, with their high operation frequency and integration density, is more aggressive than the effect obtained on devices of less advanced technologies. It can no longer be justified that a single fault only causes a single error. Consequently, it is necessary to deal with multiple errors. It has been also observed with Single Events Upsets on static and dynamic RAM memories. Moreover, thinking on the short distance existing between pads, it would be reasonable to validate the tolerance of the system against multiple faults in physically neighbouring lines.There are many fault injection techniques and tools, among them, Physical fault injection at pin level is applied externally to the system and it can fulfil the requirement of not causing overhead or alteration in the execution of the code. Thus, this technique is suitable to validate complex fault-tolerant real-time distributed embedded systems. The strong temporal requirements of a real-time system, and its own co...

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Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

Cited by 115 publications

References 10 publications

Dependability evaluation of COTS microprocessors via on-chip debugging facilities

Dependability evaluation of COTS microprocessors via on-chip debugging facilities

Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers

Validación de la arquitectura TTA mediante inyección física de fallos a nivel de PIN.

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