Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers

Ottavi, Marco; Pontarelli, Salvatore; Leandri, A.; Salsano, A.

doi:10.1109/dft.2006.21

Cited by 3 publications

(3 citation statements)

References 15 publications

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“…they are only responsible for detecting errors and no recovery mechanism was considered. In addition, latency in detecting errors in signature monitoring techniques such as [19], [21], [22] may produce irretrievable results that make recovery difficult or impossible. Furthermore, using complementary recovery techniques may incur more performance overhead.…”

Section: Introductionmentioning

confidence: 96%

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FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption

Farazmand

Fazeli

Miremadi

2008

2008 Third International Conference on Availability, Reliability and Security

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This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs) without program interruption. The proposed technique is based on the modification of application software and minor changes in the underlying hardware. To demonstrate the effectiveness of CFEDC, it has been implemented on an OpenRISC 1200 as a case study. Analytical results for three workload programs show that this technique detects all CFEs and corrects on average about 81.6% of CFEs. These figures are achieved with zero error detection /correction latency. According to the experimental results, the overheads are generally low as compared to other techniques; the performance overhead and the memory overhead are on average 8.5% and 9.1%, respectively. The area overhead is about 4% and the power dissipation increases by the amount of 1.5% on average.

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Section: Introductionmentioning

confidence: 96%

“…designing low cost CFC techniques with low overheads [19]. Although, the proposed IP core-based CFC techniques such as [19][20][21][22] provide good fault detection coverage with low overheads, they have an important common weakness, i.e. they are only responsible for detecting errors and no recovery mechanism was considered.…”

Section: Introductionmentioning

confidence: 99%

FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption

Farazmand

Fazeli

Miremadi

2008

2008 Third International Conference on Availability, Reliability and Security

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“…They have proven that while dependability is improved when using TMR, the dependability of the core is still limited by multiple factors including MBUs affecting two or three TMR domains. Another study by M. Ottavi et al [14] investigates a signature-based checker that mitigates SEUs in a complex instruction set computer (CISC): The Intel 8051 8-bit microcontroller. This checker checks the control flow integrity by analyzing the signature that is created for every sequence of instructions before every program branch.…”

Section: Introductionmentioning

confidence: 99%

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Annink

Rauwerda

Hakkennes

et al. 2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.

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