FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption

Farazmand, Navid; Fazeli, Mahdi; Miremadi, Seyed Ghassem

doi:10.1109/ares.2008.199

Cited by 13 publications

(6 citation statements)

References 19 publications

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“…In [23], checkpointing with rollback recovery and active replication is implemented to tolerate SEs at the task level. In [9], [29] techniques able to detect and correct control flow errors without a program interruption are presented. Different SW approach based on additional tasks responsible for checking other tasks is presented in [25].…”

Section: B Representatives Of Existing Workmentioning

confidence: 99%

On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

Strnadel

Slimarik

2012

2012 15th Euromicro Conference on Digital System Design

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Embedded systems as well as real-time kernels for their construction are sensitive to transient and other faults, each of which can lead to various errors at various system levels and can potentially result in the system failure. In existing works, sensitivity to transient SEU errors was studied only with the goal to classify SEU impacts to the system behavior. In this paper, the study is extended to permanent faults being injected into the persistent memory used to store the program and into the volatile memory used to store data structures. Moreover, it is studied there how the sensitivity is affected if combination of selected software-implemented fault tolerant techniques is built into the kernel and task levels of the system. The set of common fault tolerant techniques is extended to a novel watchdog-inspired technique designed to check the correctness of task executions. On the experimental basis, it is shown that the fault impacts can be softened by the proper combination of the techniques.

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Section: B Representatives Of Existing Workmentioning

confidence: 99%

On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

Strnadel

Slimarik

2012

2012 15th Euromicro Conference on Digital System Design

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“…ASIS [11] uses a hardware signature generator and watchdog monitor to check the control flow of several processors. (3) Hybrid CFC techniques [4,10,12,[34][35][36]42], in general, involve modifications of program code using a compiler, and modifications in the processor hardware, to monitor the control flow. They apply a mix of software and hardware techniques to detect CFEs.…”

Section: Control Flow Errors and Control Flow Checkingmentioning

confidence: 99%

“…They apply a mix of software and hardware techniques to detect CFEs. CFEDC [12] inserts instructions identifying branches before the branches using a compiler, and modifies the fetch and decode stages in the processor pipeline with a hardware logic to correct any errors in the instruction preceded by a hamming code of the branch instruction. SIS [35] generates instruction streams of the program code applied with signatures and monitors signatures of the sequence of executed instructions using a watchdog processor.…”

Section: Control Flow Errors and Control Flow Checkingmentioning

confidence: 99%

“…For example, as shown in Figure 1, CFCSS adds some instructions to assign a variable to a unique value (signature) in each basic block, and also adds instructions in each basic block to check if the control flow is coming from a correct predecessor basic block. Several control flow based soft error protection techniques were developed over the last few decades and span across design layers from hardware [11, 23-25, 31, 32], software [2,3,9,15,28,39,40], and hardware-software hybrid techniques [4,10,12,[34][35][36]42].…”

Section: Introductionmentioning

confidence: 99%

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Control Flow Checking or Not? (for Soft Errors)

Rhisheekesan

Jeyapaul

Shrivastava

2019

ACM Trans. Embed. Comput. Syst.

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Huge leaps in performance and power improvements of computing systems are driven by rapid technology scaling, but technology scaling has also rendered computing systems susceptible to soft errors. Among the soft error protection techniques, Control Flow Checking (CFC) based techniques have gained a reputation of being lightweight yet effective. The main idea behind CFCs is to check if the program is executing the instructions in the right order. In order to validate the protection claims of existing CFCs, we develop a systematic and quantitative method to evaluate the protection achieved by CFCs using the metric of vulnerability. Our quantitative analysis indicates that existing CFC techniques are not only ineffective in providing protection from soft faults, but incur additional performance and power overheads. Our results show that software-only CFC protection schemes increase system vulnerability by 18%-21% with 17%-38% performance overhead and hybrid CFC protection increases vulnerability by 5%. Although the vulnerability remains almost the same for hardware-only CFC protection, they incur overheads of design cost, area, and power due to the hardware modifications required for their implementations. CCS Concepts: • Computer systems organization → Reliability; • Software and its engineering → Data flow architectures; Control structures;

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“…This increases the execution time of the program and does not guarantee that all faults will be corrected. Hardware approaches typically introduce error correcting codes [9], [10], signature comparisons [11], or duplicate/triplicate hardware that is prone to faults [12], [13]. Error correcting codes can only detect and correct a limited number of bit-flips and as such do not protect all instructions in security-sensitive applications, just like signature comparisons.…”

Section: Introductionmentioning

confidence: 99%

Using Hopfield Networks to Correct Instruction Faults

Köylü

Fieback

Hamdioui

et al. 2022

2022 IEEE 31st Asian Test Symposium (ATS)

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Fault injection attacks pose an important threat to security-sensitive applications, such as secure communication and storage. By injecting faults into instructions, an attacker can cause information leakage or denial-ofservice. Hence, it is important to secure the sensitive parts not only by detecting faults in the executed instructions but also by correcting them. In this work, we propose a hardware detection and correction module based on Hopfield networks. Our module is connected to the instruction buffer and validates all fetched instructions. In case faults are detected, faulty instructions are replaced by corrected ones. Experimental results on a small RISC-V processor and two RSA implementations show that we achieve near perfect detection and around 70% accurate correction with 9% area overhead. This correction rate is enough to secure some implementations for all considered attacks.

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FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption

Cited by 13 publications

References 19 publications

On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

Control Flow Checking or Not? (for Soft Errors)

Using Hopfield Networks to Correct Instruction Faults

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