SEU characterization of hardened CMOS SRAMs using statistical analysis of feedback delay in memory cells

Geometrical factors in SEE rate calculations

“…Data furnished by Aerospace (19) Similar data has been observed with UTMC gate arrays. as it penetrates to the sensitive region so that its LET is not the surface LET (l), [2] The device has an appreciable depth so that the d correction to the cross section is not appropriate (20,1), [3] The funnel effect is important so that the cos0 correction is not appropriate for the LET calculation (21,22), [4] Two ions of same nominal LET may have entirely Merent track structure, so that the effective area of device plus track changes (23).…”

Band gap engineered resistor for mitigating linear energy transfer sensitivities in scaled submiron CMOS technology SRAM cells

“…High value polysilicon resistors have traditionally been used to introduce the feedback delay [1]. When an SEU event disturbs a vulnerable node, the RC delay to the other inverter of the cell postpones the complete state change of the cell, giving the restoring ''on" transistor time to recover the disturbed node.…”

Flip-flop hardening for space applications

“…-G or Gb nodes can be upset if they store a 1 either through the mt1 or mr2 junctions or through the mt2 or mr1 junctions. To prevent a possible upset on the Q or Qb node, the concept of feedback polysilicon resistors [5] has been used. In our case the resistors are just replaced by MOS.…”

“…In the second case the pulse surges in the Dlatch working as an isolated memory point. So, if charges collection conditions are fulfilled [4,5], it can change the logical state of the cell. This effect can be referred as "static SEU" or "sequential error".…”