Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers.. .) that make up the circuit. In this paper, we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model will consequently be dependent on this sensitivity.
The purpose of this work is to design a Flip-flop hardened to Single Event Upset (SEU) for space radiation environment. The design hardening technique is based on the use of two Dlatch hardened both to static and dynamic SEU by the concepts of high impedance state and nMOS feedback.
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