Supply voltage glitches effects on CMOS circuits

Abstract

Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers.. .) that make up the circuit. In this paper, we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model will consequently be dependent on this sensitivity.

Injecting Software Vulnerabilities with Voltage Glitching

“…One level down from that is the paper by Djellid-Ouar, Cathebras and Bancel [4] which concluded that D-flip-flops This work was not supported and do not represent the approval or rights of any third parties. 1.…”

“…A faster clock will increase the chance of a successful fault (due to timing violations). In practice, we cannot over-clock much past the default rate of 37MHz or we will run into non-voltage glitch related timing violations that prevent the circuit from working properly 4 . However, in our case, because of the noisy design of our glitching setup, we picked f = 12 MHz since it was the fastest we were able to go without running into a variety of signal integrity issues.…”

The Forgotten Threat of Voltage Glitching: A Case Study on Nvidia Tegra X2 SoCs

“…This dependency can be misused to force faulty behavior during the chip's operation. Short supply voltage variations, introduced by glitches on the supply voltage line, can produce computational errors in CMOS circuits [9]. Examples of such errors are memory bit flips, corrupted instructions, and jumping over instructions in a microprocessor.…”

“…A simpler approach to inject faults into the system is voltage FI, where the supply voltage is over-or undervolted for a short moment [9]. The technique is also referred to as voltage glitching.…”

Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism

“…However, very few papers have been dedicated to a deep investigation of the underlying fault injection mechanism. The most significant paper [9] studied accurately the effects of a voltage glitch on the DFFs of a CMOS circuit. It showed, on a simulation basis, that power supply glitches cannot induce faults into DFFs.…”