SEU characterization of a hardened CMOS 64K and 256K SRAM

Abstract

The first single-event-upset (SEU) tests of the A T & T 6 4 K a n d 2 5 6 K S R A M s h a v e b e e n performed. Feedback resistor values for these parts ranged from 200kQ to IMQ. All were fabricated using the 1-pm 2-level poly, 2-level metal process. Ions used for these tests were Ar, Cu, Kr, and Xe providing a range of effective LET values from 20 to 129 MeV-cm2/mg. With t h e 64K S R A M operating at 4.5 volts and 90°C, an upset threshold LET of 30 MeV-cm2/mg and saturation crosssection of 1.5 x cm2 were measured with a nominal room temperature feedback resistance of 450kn. In Adam's 10% worst-case environment using the Petersen approximation, this implies an error rate of 1.3 x errors per bit-day. With a nominal 650kQ feedback resistance, a 256K SRAM had a calculated error rate of about 3 x 10-8 errors per bit-day at 4.5 volts and 90°C. This data agrees well with earlier data for a 1K-bit test chip. The minimal feedback resistance required to prevent upset vs. L E T is calculated by assuming an activation energy of 0.10 e V to estimate the decrease in feedback resistor value as a function of temperature.

Temperature dependence of neutron-induced soft errors in SRAMs

“…According to the information we gathered from the datasheets, all the SRAMs feature 6-T cells, so the observed changes are not related to increasing resistance of the pull-up resistors as in Ref. [8].…”

“…Only few works in the literature analyzed temperature effects on SER [7][8][9]. Some conclude that temperature plays a marginal role in determining the critical charge in SRAMs and, in general, the SER [7].…”

“…Some conclude that temperature plays a marginal role in determining the critical charge in SRAMs and, in general, the SER [7]. Sexton et al observed an increased SEU sensitivity at high temperature in hardened memories and attributed this behavior to variations in the conductivity of the feedback and load resistors [8]. Truyen et al performed TCAD simulations of heavyion strikes in 180-nm 6-T cells as a function of temperature [9].…”

Single Event Upset Mechanisms for Low-Energy-Deposition Events in SiGe HBTs

“…Five general explanations have been proposed in the literature: 1) energy loss of the ion before arriving at the surface of the device, changing its LET [25], 2) the device has significant collection depth so that the cos(θ) correction to the cross section doesn't hold [33] Germanium introduced [12]. Introducing an alloy of SiGe in the base of a bipolar transistor provides a valence band offset in the base (Fig.…”

Influence of edge effects on single event upset susceptibility of SOI SRAMs

“…In fact, the influence of tilted irradiations of heavy ions on the charge collection at PN junctions and SOI transistor has also been investigated by other authors [13][14][15]. The approach of upset correction by cosðhÞ appears to result in different cross-sections for deeper devices for the same effective LET [16][17][18][19]. Petersen et al [20] attributed the inapplicability of upset cross-section corrected by cosðhÞ to the edge effects which is induced by ions through the edge of sensitive region, and proposed an approach to correct the impact of edge effects on upset cross-section at tilted incidence.…”