Sequential Equivalence Checking by Symbolic Simulation

Ritter, Gerd

doi:10.1007/3-540-40922-x_26

Cited by 4 publications

(4 citation statements)

References 12 publications

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“…The simulator is based on the method shown in [1], which verifies the equivalence of RTL or gate level descriptions in HDL. We modify the method for the verification of C-based design descriptions in word-level.…”

Section: A Basic Proceduresmentioning

confidence: 99%

Equivalence checking of high-level designs based on symbolic simulation

Matsumoto

Nishihara

Kojima

et al. 2009

2009 International Conference on Communications, Circuits and Systems

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In this paper, we present a formal equivalence checking method for source-to-source refinements in C-based high-level hardware design descriptions. The method is based on word-level symbolic simulation, where variables and operators in designs are treated as uninterpreted symbols. In addition, we introduce a more efficient method utilizing the difference between two designs under verification. It can verify the equivalence faster when the similarity between the designs is large. We also show case studies of equivalence checking that were carried out with our verification framework FLEC.

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Section: A Basic Proceduresmentioning

confidence: 99%

Equivalence checking of high-level designs based on symbolic simulation

Matsumoto

Nishihara

Kojima

et al. 2009

2009 International Conference on Communications, Circuits and Systems

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“…Since schedulings of executions are totally different between behavioral and RTL descriptions, it is not so obvious to define what is the "equivalence" between them. Therefore, direct use of the methods in Currie et al [2000], Ritter [2000], and Matsumoto et al [2004] cannot work as they are for the equivalence checking between behavioral and RTL descriptions. This situation also holds in the case of equivalence checking between two behavior descriptions and between two RTL descriptions, since it is often the case that only limited similarity and hence very little internal equivalence appears in the two descriptions to be compared.…”

Section: Introductionmentioning

confidence: 97%

“…In particular, equivalence checking between behavioral level and register transfer level (RTL) description is one of the most important issues when supporting higher-level designs, although so far there have been only a limited number of works on it [Semeria et al 2002;Clarke et al 2003]. There have been works on equivalence checking targeting two similar high-level descriptions such as, Currie et al [2000], Ritter [2000], and Matsumoto et al [2004]. They are based on symbolic simulation and utilize This research was supported by the Funding Agency.…”

Section: Introductionmentioning

confidence: 98%

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths

Fujita

2005

ACM Trans. Des. Autom. Electron. Syst.

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In this article, we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed "attribute statements" in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are also presented.

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“…Other researchers had to limit the data values to 4 bits, the register file to 1 register, and the ISA to 16 symbolically verify a bit-level pipelined processor 136 . Various symbolic tools ran for a long time when formally verifying a pipelined DLX [137][138][139][140] , or ran out of memory 141 . Custom-tailored, manually defined rewriting rules were used to formally verify a 5-stage DLX 142,143 , and similar 4-stage processors [144][145][146][147] , but would require modifications to work on designs described in different coding style, and significant extensions to scale for dual-issue superscalar processors.…”

Section: Related Workmentioning

confidence: 99%

Integrating Formal Verification Into An Advanced Computer Architecture Course

Velev

2003 Annual Conference Proceedings

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The paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors. The projects were integrated-by means of lectures and preparatory homework exercises-into an existing advanced computer architecture course taught to both undergraduate and graduate students in a way that required them to have no prior knowledge of formal methods. The first project was on design and formal verification of a 5-stage pipelined DLX processor, implementing the six basic instruction types-register-register-ALU, registerimmediate-ALU, store, load, jump, and branch. The second project was on extending the processor from project one with ALU exceptions, a return-from-exception instruction, and branch prediction; each of the resulting models was formally verified. The third project was on design and formal verification of a dual-issue superscalar version of the DLX from project one. The preparatory homework problems included an exercise on design and formal verification of a staggered ALU, pipelined in the style of the integer ALUs in the Intel Pentium 4. The processors were described in the high-level hardware description language AbsHDL that allows the students to ignore the bit widths of word-level values and the internal implementations of functional units and memories, while focusing entirely on the logic that controls the pipelined or superscalar execution. The formal verification tool flow included the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker; this tool flow-combined with the same abstraction techniques for defining processors with exceptions and branch prediction, as used in the projects-was applied at Motorola to formally verify a model of the M•CORE processor, and detected bugs. The course went through two iterations-offered at the Georgia Institute of Technology in the summer and fall of 2002-and was taught to 67 students, 25 of whom were undergraduates.

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Sequential Equivalence Checking by Symbolic Simulation

Cited by 4 publications

References 12 publications

Equivalence checking of high-level designs based on symbolic simulation

Equivalence checking of high-level designs based on symbolic simulation

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths

Integrating Formal Verification Into An Advanced Computer Architecture Course

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