Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

Si/Ge hetero-structure nanotube tunnel field effect transistor

“…Secondly, both the normalized "ON" current and SS degrade when NWs are arrayed due to sensitivity of parameters like threshold voltage to, for example, variations in NW width, dielectric thickness, and effective gate length, which could lead to degradation of the SS swing for a large array of devices, especially when considering highly doped source and drain junctions. 22,23 Thirdly and most importantly, the state-of-the-art pitch for vertical NW does not offer high current per unit chip area, as has been shown in the recent demonstrations showing NW pitch in the order of 400 nm for both top down 23 and bottom up approaches. 24 On the other hand, I ON ¼ 100lA/lm at V DD ¼ 1.0 V and V GS ¼ 1 V for all-silicon single gated SOI based TFETs with vertical self-aligned top gate structure supplying and for 70 nm thick SOI with 2 nm effective oxide thickness.…”

Electrical characterization of high performance, liquid gated vertically stacked SiNW-based 3D FET biosensors

“…The threshold voltage Vth is defined as the voltage for which the drain current reaches a value of = (100 * / ) as it is typically defined in industry [23].…”

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

“…To validate the choice of model/method taken in modeling and simulation, the calibration of simulated results with the experimental results of Choi et al [28] is performed and it is shown in Fig. 1(f).…”