Self-timed adder with pipelined output

Abstract

This paper presents the design of a self-timed adder, with event driven logic and pipelined output. The scheme makes the individual outputs of bit-wise additions independent of the preceding bits, resulting in high throughput at the cost of initial latency and hardware overheads. Simulation results based on parameters extracted from VLSI implementation of a model 4-bit adder are used to illustrate the performance. The design was implemented with transmission gates in 2-micron CMOS technology. Expansibility to larger adders is shown to give the same performance benefits.