Self-reparable system on FPGA for single event upset recovery

Legat, Uroš; Biasizzo, Anton; Novak, Franc

doi:10.1109/recosoc.2011.5981512

Cited by 6 publications

(2 citation statements)

References 10 publications

(13 reference statements)

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“…On the other hand, standard coarse-grained TMR architectures [5], [13], [14] use only one voter partition in order to propagate the correct result as shown in Fig. 1b.…”

Section: Related Workmentioning

confidence: 99%

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures

Veljković

Riesgo

Torre

2015

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Abstract-The impact of SRAM-based FPGAs is constantly growing in aerospace industry despite the fact that their volatile configuration memory is highly susceptible to radiation effects. Therefore, strong fault-handling mechanisms have to be developed in order to protect the design and make it capable of fighting against both soft and permanent errors. In this paper, a fully reconfigurable medium-grained triple modular redundancy (TMR) architecture which forms part of a runtime adaptive onboard processor (OBP) is presented. Fault mitigation is extended to the voting mechanism by applying our reconfiguration methodology not only to domain replicas but also to the voter itself. The proposed approach takes advantage of adaptive configuration placement and modular property of the OBP, thus allowing on-line creation of different medium-grained TMRs and selection of their granularity level. Consequently, we are able to narrow down the fault-affected area thus making the error recovery process faster and less power consuming. The conventional hardware based voting is supported by the ICAPbased one in order to additionally strengthen the reconfigurable intermediate voting. In addition, the implementation methodology ensures using only one memory footprint for all voters and their voting adaptations thus saving storing resources in expensive rad-hard memories.

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“…On the other hand, standard coarse-grained TMR architectures [5], [13], [14] use only one voter partition in order to propagate the correct result as shown in Fig. 1b.…”

Section: Related Workmentioning

confidence: 99%

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures

Veljković

Riesgo

Torre

2015

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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“…Using a good external WDT, such as a periodic reset monitor (PRM), to switch the power to the system based on a programmed time will solve this problem [11][12]. Some applications of external WDTs are used in fieldprogrammable gate arrays (FPGA) [13][14] or commercial offthe-shelf (CTOS) processor based systems [15].…”

Section: Introductionmentioning

confidence: 99%

Design of a dual-microcontroller scheme to overcome the freeze problem for a smart data logger

Mahendra

Syamsi

2014

2014 2nd International Conference on Information and Communication Technology (ICoICT)

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Screen freeze (or no response) is a condition that often occurs in a Personal Computer (PC). In this condition, the PC has lost the ability to respond to its application programs. The same thing can also happen to a data logger, which is usually constructed by using a microcontroller or embedded processor. We propose a design of a dual microcontroller to overcome hang, or no response, of the main microcontroller in a data logger. One of the smart features is an auto restart or reboot, so the data logger with the 'no response' condition is able to reboot without operator assistance. We used an ATmega128 as the main or master microcontroller and an ATtiny13 as the watchdog or slave microcontroller. The watchdog microcontroller detects the activity of the main microcontroller by monitoring a periodic signal from the main microcontroller. If a disruption occurs in the system and the main microcontroller is not able to send this periodic signal, the watchdog microcontroller would determine that a system failure has occurred. System failure will trigger the watchdog microcontroller to activate a relay to reset the main microcontroller. This capability is expected to increase the stability of the data logger and minimize the measurement data lost.

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