Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory

Mukhopadhyay, Saibal; Kim, Keejong; Mahmoodi, Hamid; Datta, Animesh; Park, Dongkyu; Roy, Kaushik

doi:10.1109/vlsic.2006.1705345

Cited by 9 publications

(6 citation statements)

References 1 publication

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“…Self-repairing SRAM [1] improves the operating margins using body-bias control technique. Mismatch of threshold voltage in cells of a SRAM memory array causes degradation in operating margins in SOC chips.…”

Section: The Effect Of Process Variationsmentioning

confidence: 99%

“…Mismatch of threshold voltage in cells of a SRAM memory array causes degradation in operating margins in SOC chips. Self-repairing SRAM [1] improves the operating margins using body-bias control technique. Also, body biasing of NMOS and PMOS transistors cell compensates threshold voltage variations that are caused by manufacturing process fluctuations [3].…”

Section: The Effect Of Process Variationsmentioning

confidence: 99%

“…The previously proposed SRAMs often tried to improve the thier parameters using new architectures or peripheral circuits via body biasing [1][2][3][4][5][6]. The previously proposed SRAMs often tried to improve the thier parameters using new architectures or peripheral circuits via body biasing [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

“…In the recent years, many efforts are made to control the threshold voltage using body biasing to improve the performance of SRAM cell. The previously proposed SRAMs often tried to improve the thier parameters using new architectures or peripheral circuits via body biasing [1][2][3][4][5][6]. Usually, these circuits with additional transistors can reduce the power dissipation or improve the timing performance [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

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New SRAM design using body bias technique for low‐power and high‐speed applications

Faraji¹,

Naji²,

Rahimi-Nezhad³

et al. 2013

Circuit Theory & Apps

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In this paper, a new SRAM cell with body-bias actively controlled by a control circuit and word line is introduced to realize low-power and high-speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade-off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%.

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Section: The Effect Of Process Variationsmentioning

confidence: 99%

Section: The Effect Of Process Variationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

New SRAM design using body bias technique for low‐power and high‐speed applications

Faraji¹,

Naji²,

Rahimi-Nezhad³

et al. 2013

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…The testing community has developed methods to repair manufacturing faults using redundant rows and columns to improve yield [7,8,13,14,22]. It is a well-known NP-complete problem with a limited set of row/column redundancies.…”

Section: Introductionmentioning

confidence: 99%

Leakage-aware redundancy for reliable sub-threshold memories

Kim

Guthaus

2011

Proceedings of the 48th Design Automation Conference

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NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

Kang

Gangwal

Park

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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-This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. For improved lifetime stability, we propose/select an efficient reliability-aware circuit design methodologies. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. As a result, simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells. Hence, aggressive design techniques such as stand-by V DD scaling or adaptive body biasing (ABB) are required in memory application to minimize the impact of NBTI.

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Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory

Cited by 9 publications

References 1 publication

New SRAM design using body bias technique for low‐power and high‐speed applications

New SRAM design using body bias technique for low‐power and high‐speed applications

Leakage-aware redundancy for reliable sub-threshold memories

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

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