NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

Abstract

-This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. For improved lifetime stability, we propose/select an efficient reliability-aware circuit design methodologies. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. As a result, simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells. Hence, aggressive design techniques such as stand-by V DD scaling or adaptive body biasing (ABB) are required in memory application to minimize the impact of NBTI.

Signal probability control for relieving NBTI in SRAM cells

“…If diffusing species is H, n is 1/4 and if diffusing species is H 2 , n is 1/6 [8]. In the reaction of breaking S i − H bonds, H 2 tends to be dominant [8], [14]. Therefor, we use the time exponent value of 1/6.…”

“…There are two load PMOS transistors (P1 and P2). Due to NBTI degradation, the threshold voltage degrades in the load PMOS transistors [6], [8], [9]. As a result the read stability degrades in an SRAM cell.…”

“…Therefore, we can't decide on the suitable mode switching cycle. r e g [ 1 ] r e g [ 2 ] r e g [ 3 ] r e g [ 4 ] r e g [ 5 ] r e g [ 6 ] r e g [ 7 ] r e g [ 8 ] r e g [ 9 ] r e g [ 1 ] r e g [ 2 ] r e g [ 3 ] r e g [ 4 ] r e g [ 5 ] r e g [ 6 ] r e g [ 7 ] r e g [ 8 ] r e g [ 9 ] Given this factor, we focus on the Mean Cycle to Reading (MCTR). It is shown in Figure 7.…”

“…In an SRAM cell, NBTI causes read stability degradation [6], [8], [9]. Static Noise Margin(SNM) is one of the measures of read stability.…”

Implications of accelerated self-healing as a key design knob for cross-layer resilience

“…based on application behaviors) and design margin is reserved by adding guardband at the circuit level (e.g. oversizing), it has been shown in [2], [9], [10] that the margin can be > 20% for a 10-year lifetime constraint, the added margins usually lead to large timing slacks and therefore wasteful power consumption especially during the initial lifetime. A second solution would be adaptive techniques during run time, where wearout induced variations are tracked and monitored by sensors, then various actuators are employed for compensating or adapting to the variations dynamically [11], [12], so the system is able to be designed for the average case.…”