Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Zebulum, R.; Mojarradi, M.; Stoica, Adrian; Keymeulen, Didier; Daud, T.

doi:10.1109/ahs.2007.96

Cited by 3 publications

(4 citation statements)

References 5 publications

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“…In the experiments conducted, the GA core found atleast one globally optimal solution for many different parameter settings as shown in bold in Table VI. The authors also observed that the GA core found atleast two different globally optimal solutions, (x 1 =C2, y 1 =4A) and (x 2 =DB,y 2 =4A), during the experimental run with RNG seed=(AAAA) 16 , population size=64, and crossover threshold=10. Figure 9.…”

Section: Modified 2d Shubert Functionmentioning

confidence: 87%

“…This can be very useful in space and military applications where human intervention needs to be minimized. In [16], Zebulum et al proposed a Self-Reconfigurable Analog Array (SRAA) architecture that used multiple building blocks to build different analog circuits including Pulse Width Modulator, Power Switch Control, Shaft Encoder, and Instrumentation Amplifier. They identified a list of analog building blocks such as Op-Amps, Low offset Op-Amps, High Voltage Op-Amp, Current Source, Comparator, and High-speed Comparator and implemented them in as a Reconfigurable Analog Array ASIC.…”

Section: Self Reconfigurable Analog Electronicsmentioning

confidence: 99%

“…In the experiments conducted, the best candidate found by the GA core for the mBF7_2 test function was 65516. The corresponding solution is y=(FF) 16 and x=(EC) 16 with a fitness of 61496. This is…”

Section: Popsize=32mentioning

confidence: 99%

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Programmable genetic algorithm IP core for sensing and surveillance applications

et al. 2009

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Real-time evolvable systems are possible with a hardware implementation of Genetic Algorithms (GA). We report the design of an IP core that implements a general purpose GA engine which has been successfully synthesized and verified on a Xilinx Virtex II Pro FPGA Device (XC2VP30). The placed and routed IP core has an area utilization of only 13% and clock speed of 50MHz. The GA core can be customized in terms of the population size, number of generations, cross-over and mutation rates, and the random number generator seed. The GA engine can be tailored to a given application by interfacing with the application specific fitness evaluation module as well as the required storage memory (to store the current and new populations). The core is soft in nature i.e., a gate-level netlist is provided which can be readily integrated with the user's system. The GA IP core can be readily used in FPGA based platforms for space and military applications (for e.g., surveillance, target tracking). The main advantages of the IP core are its programmability, small footprint, and low power consumption. Examples of concept systems in sensing and surveillance domains will be presented.

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Section: Modified 2d Shubert Functionmentioning

confidence: 87%

Section: Self Reconfigurable Analog Electronicsmentioning

confidence: 99%

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Programmable genetic algorithm IP core for sensing and surveillance applications

et al. 2009

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“…In particular, it is possible to distinguish between analog EHW systems, mixed analogdigital EHW systems, and digital EHW systems. Analog EHW systems are based on either Field Programmable Transistor Arrays (FPTA) or Field Programmable Analog Arrays (FPAA) [Terry et al 2006;Zebulum et al 2007]. Mixed analog-digital EHW systems, instead, rely on custom devices (e.g., the Evolvable Motherboard described by Layzell [1998]) and can be used to develop circuits composed of both digital and analog parts.…”

Section: Evolvable Hardware: Taxonomymentioning

confidence: 99%

On the Evolution of Hardware Circuits via Reconfigurable Architectures

Cancare

Bartolini

Carminati

et al. 2012

ACM Trans. Reconfigurable Technol. Syst.

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Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed-the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature.FPGA-based approaches have emerged as the main architectural solution to implement EHW systems. Various EHW systems have been proposed by researchers but most of them, being based on outdated chips, do not take advantage of the interesting features introduced in newer FPGAs. This article describes a project named Hardware Evolution over Reconfigurable Architectures (HERA), which aims at creating a complete and performance-oriented framework for the evolution of digital circuits, leveraging the reconfiguration technology available in FPGAs. The project is described from its birth to its current state, presenting its evolutionary technique tailored for FPGA-based circuits and the most recent enhancements to improve the scalability with respect to problem size. The developed EHW system outperforms the state of the art, proving its effectiveness in evolving both standard benchmarks and more complex real-world applications.

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