On the Evolution of Hardware Circuits via Reconfigurable Architectures

Abstract

Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed-the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature.FPGA-based approaches have emerged as the main architectural solution to implement EHW systems. Various EHW systems have been proposed by researchers but most of them, being based on outdated chips, do not take advantage of the interesting features introduced in newer FPGAs. This article describes a project named Hardware Evolution over Reconfigurable Architectures (HERA), which aims at creating a complete and performance-oriented framework for the evolution of digital circuits, leveraging the reconfiguration technology available in FPGAs. The project is described from its birth to its current state, presenting its evolutionary technique tailored for FPGA-based circuits and the most recent enhancements to improve the scalability with respect to problem size. The developed EHW system outperforms the state of the art, proving its effectiveness in evolving both standard benchmarks and more complex real-world applications.

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

“…The top-down approach using DPR would require at least 2 8×64 bitstreams to be stored in unavailable large external memories considering the case when one PE is implemented in a reconfigurable module. Table II shows the resource utilization of the implementation in the column "Proposed DPR" and compares it with the VRC [Dobai and Sekanina 2013a] and module-based DPR implementations. As it can be observed, the area required by the proposed method is smaller than for the VRC.…”

“…A similar architecture was proposed by Cancare et al [2012]. It supports the evolution at various levels of hierarchy (e.g., logic gates, functional blocks).…”

“…Recently, a hybrid approach was proposed for EHW that adopts the advantages of the native and virtual reconfigurations while limiting their disadvantages [Dobai and Sekanina 2013a]. The name reflects the fact that both types of reconfiguration are necessary to establish a given candidate solution.…”

“…The work presented in this article uses a hybrid approach merging their advantages (flexibility, speed of evolution, area overhead) while limiting the disadvantages. Although the hybrid approach was first used for EHW in Dobai and Sekanina [2013a], the complete implementation and evaluation including the statistical results and evolved examples are the subject of this work only.…”

Lookup table partial reconfiguration for an evolvable hardware classifier system

“…An approach to online EHW classification on FPGAs can be found in [18], [19], where an on-chip system including a PowerPC processor initiates partial reconfiguration on the classifier sub-system. The system uses a direct bitstream manipulation approach to reconfigure a hierarchical two-dimensional array structure.…”