Self- heating effects in SOI MOSFET transistor and numerical simulation using Silvaco software

FZ.Rahou,; Bouazza, A. Guen; Rahou, M.

doi:10.1109/icm.2012.6471454

Cited by 6 publications

(3 citation statements)

References 4 publications

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“…To respond to these challenges, researchers have proposed new structures for FDSOI MOSFET, such as variations in doping on the source side and the formation of pockets in the FDSOI MOSFET [10,11]. Moreover, in the construction of digital integrated circuits, there has been some speculation [12,13] that FDSOI MOSFETS might be utilized as an alternative to conventional bulk MOS transistors. In this study, we provide a novel construction for an SOI MOSFET that reduces the off-state current and sub-threshold slope, in contrast to a normal FDSOI structure with the integration of germanium in the source and drain pockets.…”

Section: Introductionmentioning

confidence: 99%

Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

Singh,

Mishra,

Akhter

2024

Eng. Res. Express

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This study investigates the electrical performance of advanced semiconductor Ge-pocket-doped fully depleted silicon-on-insulator MOSFETs in comparison to conventional fully depleted silicon-on-insulator (FDSOI) MOSFETs. In this study vital electrical parameters such as the drain current, band diagram, lateral electric field, surface potential, and work function of the gate material were investigated. The advanced Ge pocket-doped FDSOI MOSFET structure demonstrates superior characteristics, such as a higher Ion/Ioff ratio, smaller subthreshold slope, lower capacitance, and higher cut-off frequency, when compared to conventional FDSOI MOSFETs. The structure of the Ge pocket-doped FDSOI MOSFET in the source and drain regions is designed to overcome the scaling effects of the transistor. In addition, this paper delves into the fabrication of the proposed device structure, outlining the key steps and intricacies involved. This study shows that the proposed device can be used for both digital and analog applications because it has good switching performance and a low cut-off frequency. In addition, the fabrication steps of the proposed structure were compatible with the existing fabrication process steps for conventional FDSOI MOSFETs. The simulation and analysis of the advanced semiconductor structure were performed using the Sentaurus TCAD simulator.

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Section: Introductionmentioning

confidence: 99%

Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

Singh,

Mishra,

Akhter

2024

Eng. Res. Express

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“…Enormous research work has been done in semiconductor industry for the accommodation of more complex circuits on a single semiconductor substrate. To accomplish this purpose the feasible method is device scaling [1]. There is continual scaling down of MOSFET size [2].…”

Section: Introductionmentioning

confidence: 99%

Simulation Study of 50 nm Gate Length MOSFET Characteristics

Chowdhury¹

2023

AMPC

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With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silvaco TCAD Tool so as to observe various electrical parameters at this gate length. The parameters under investigation are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL) by varying channel doping concentration, drain and source doping concentration and gate oxide thickness.

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“…Mesmo com todas as vantagens citadas acima, a tecnologia SOI apresenta um problema bastante notável, sendo este a dificuldade da dissipação de calor, devido à espessa camada de óxido. Este problema gera um fenômeno conhecido como autoaquecimento 4,13 , que leva a alterações nas propriedades físicas do transistor quando aquecido, gerando ciclos de elevação de temperatura. Os problemas relacionados à temperatura podem causar falhas em dispositivos que utilizam esta tecnologia.…”

Section: Introductionunclassified

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Self- heating effects in SOI MOSFET transistor and numerical simulation using Silvaco software

Cited by 6 publications

References 4 publications

Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

Simulation Study of 50 nm Gate Length MOSFET Characteristics

Ruído telegráfico em transistores sem junções

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