Simulation Study of 50 nm Gate Length MOSFET Characteristics

Abstract

With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silvaco TCAD Tool so as to observe various electrical parameters at this gate length. The parameters under investigation are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL) by varying channel doping concentration, drain and source doping concentration and gate oxide thickness.