Self-aligned metal source/drain InP n-metal-oxide-semiconductor field-effect transistors using Ni–InP metallic alloy

Kim, Sang-Hyeon; Yokoyama, Masafumi; Taoka, Noriyuki; Iida, Ryo; Lee, Sung-Hoon; Nakane, Ryosho; Urabe, Yuji; Miyata, Noriyuki; Yasuda, Tetsuji; Yamada, Hisashi; Fukuhara, Noboru; Hata, Masahiko; Takenaka, Mitsuru; Takagi, Shinichi

doi:10.1063/1.3597228

Cited by 35 publications

(45 citation statements)

References 11 publications

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“…Recently, we have found that a Ni-InGaAs alloy formed by direct reaction of Ni and InGaA is one of the materials allowing us to fabricated self-aligned metal S/D structures for InGaAs MOSFETs [28][29][30]. We have also confirmed that the same process is applicable to InP [31]. [28,29] The sheet resistance of the Ni-InGaAs alloy layers, formed by direct reaction of Ni and InGaAs, was determined by TLM patterns on p-InGaAs (1×10 16 cm -3 ).…”

Section: S/d Formationsupporting

confidence: 66%

(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS

et al. 2011

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MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to III-V and Ge channels. Thus, one of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs. In this presentation, we focus on the possible solutions for realizing CMOS integration of III-V and Ge MOSFETs. The high quality III-V channel formation on the Si platform is very challenging. In order to realize the integration of III-V/Ge MOSFETs, the direct wafer bonding is a promising way. The gate stack formation is also a critical issue for III-V/Ge CMOS integration. We have employed Al 2 O 3 gate insulators for both InGaAs and Ge MOSFETs. This is partly because ALD Al 2 O 3 is known to prove superior interface properties in InGaAs MOS structures. Also, we have recently realized Al 2 O 3 /GeO x /Ge MOS gate stacks with low D it and thin EOT by employing ALD thin Al 2 O 3 and successive plasma oxidation. Another concern in the integration process of III-V and Ge MOSFETs is S/D formation. We consider that metal S/D scheme can be the best solution for III-V/Ge CMOS. We have implemented Ni-based metal S/D technologies for both InGaAs and Ge MOSFETs. By employing these technologies described above, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

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Section: S/d Formationsupporting

confidence: 66%

(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS

et al. 2011

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“…A possible reason for roughened surface would be related to the phase change and lattice constant change with annealing temperature [43]. Sequential annealing at high temperature after first annealing at low temperature may be helpful to alleviate morphology issue as one can see from silicide and Ni-InP technologies [17], but it seems to be not so effective for Ni-InGaAs system [18].…”

Section: Thermally Stable Contact Design With a Low Specific Conmentioning

confidence: 99%

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Kim

Shin

et al. 2019

IEEE J. Electron Devices Soc.

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Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled transistors. In this paper, we demonstrate an innovative use of a heat-dissipating shunt of Ni-InGaAs on InGaAs(111) in the S/D extension region, as well as the use of high-conductivity Mo contact to simultaneously improve electrical and thermal stability and heat dissipation in III-V transistors, such that the peak channel temperature is reduced by as much as 25%-30%. Given the exponential temperature sensitivity of transistor reliability, heat shunts will improve transistor lifetime significantly.

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“…Another alternative to highly doped S/D regions is the use of metal S/D structure for III–V MOSFETs, and has been successfully explored in recent years. For InP channel MOSFETs, Ni–InP alloy S/D has been demonstrated to be very promising with low sheet resistance compared to

n^{+}

doped InP S/D and low Schottky barrier height (), analogous to Ni–InGaAs S/D for InGaAs MOSFETs (). It is interesting to note that some works have reported inherent benefits with InP source and/or drains for analog applications.…”

Section: Inp Device Performancementioning

confidence: 99%

Atomistic study of band structure and transport in extremely thin channel InP MOSFETs

Dutta

Kumar

Rastogi

et al. 2016

Phys. Status Solidi A

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Abstractauthoren III–V channel materials have emerged as one of the major contenders to replace silicon as the channel material in sub‐10 nm transistors. Motivated by this, we study the feasibility of using InP as a channel material in extremely scaled MOSFETs. In this work, we have performed a comprehensive analysis of the band structure of extremely thin InP channels with different surface orientations and transport directions using first‐principle density functional theory calculations. We show that the effective masses in the Γ valley and the bandgap increase monotonically as the thickness decreases for each orientation. Valley symmetry is found to be orientation dependent. Further, the performance of extremely thin InP channel double‐gate MOSFET is analyzed via semi‐classical as well as full quantum ballistic transport simulations using the non‐equilibrium Green's function (NEGF) approach.

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Self-aligned metal source/drain InP n-metal-oxide-semiconductor field-effect transistors using Ni–InP metallic alloy

Cited by 35 publications

References 11 publications

(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS

(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Atomistic study of band structure and transport in extremely thin channel InP MOSFETs

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