Self Aligned Barrier Approach: Overview on Process, Module Integration and Interconnect Performance Improvement Challenges

Abstract

Self aligned barriers approaches are widely investigated because they lead to a strong improvement of the Cu/barrier interface adhesion generally considered as the limiting factor for the electromigration performance of Cu interconnects capped with dielectric barriers. In this paper, several ways to perform self aligned barrier integration, using either Cu line surface treatments or selective deposition process on top of Cu lines and their basic performance are detailed. Achieved electrical and reliability performance are discussed in terms of process, integration feasibility and related issues, and architecture (stand-alone or bi-layered stack) since the self aligned barriers can be introduced at different levels of complexity depending on the performance targets and the applications foreseen.

Copper Metal for Semiconductor Interconnects

“…Therefore, to obtain a long EM lifetime, the improvement of Cu interface is the most effective method by increasing the adhesion between these layers [90]. A typical dielectric capping process consists of two main steps: plasma clean to remove Cu oxides and a Cu barrier dielectric deposition (either SiN or SiCN) [91,92]. Reproduced with permission from Ref.…”

Process Technology for Copper Interconnects

“…A further reduction in interface diffusion can be achieved by using a metal capping layer (Figure 8.21E-G) rather than a dielectric capping layer [123,128,129,131]. Improvements in electromigration lifetime of over 300 have been reported with a CoWP cap [131].…”

Effect of CoWP Capping Layers on Dielectric Breakdown of SiO<inf>2</inf>

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reduced lifetime for time dependent dielectric breakdown Abstract (TDDB), associated with surface contamination and loss of selectivity [10][11][12][13]. This problem is especially for CMOS Leakage and dielectric breakdown of SiO2 are studied for imager applications, where thick capping layers are required Cu interconnect structures with either stand-alone CoWP or [9].

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