Selective Epitaxy of Si[sub 1−x]Ge[sub x] Layers for Complementary Metal Oxide Semiconductor Applications

Abstract

The selective growth of Si-buffer/Si 1Ϫx Ge x /Si-cap structures (0.14 Ͻ x Ͻ 0.33) on patterned substrates aimed for channel layer applications in a metal-oxide-semiconductor field effect transistor structure was investigated. By optimizing the growth parameters the surface roughness of these structures was reduced. Furthermore, selective epitaxy of high B-or P-doped SiGe layers for source/drain applications was also studied. Abrupt dopant profiles with a good epitaxial quality and low sheet resistances, e.g., 195 and 260 ⍀/ᮀ for 420 Å thick, B-doped Si 0.81 Ge 0.19 and P-doped Si 0.71 Ge 0.29 layers, respectively, were obtained. In this study, secondary ion mass spectroscopy, high-resolution reciprocal lattice mapping, atomic force microscopy, and cross-sectional transmission electron microscopy were used as the main characterization tools.

Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains

“…Quite the opposite is found for phosphorus-doped Si or SiGe layers, with a growth rate which is dramatically reduced with high amounts of phosphine sent onto the growing surface, in agreement once again with Ref. [12] results (from 9.5 down to 3.6 nm min À1 for Si:P, and 9.4 from down to 3.1 nm min À1 for SiGe:P). Another point which strongly needs to be highlighted is that the SiGe growth rates at 700 C are more or less equal to the Si growth rates at 800 C, which is another big incentive (apart from the resistivity gains) to move from Si to SiGe (in order to minimize the thermal budget the device will be submitted to during the formation of these RSDs).…”

“…8a [12], the heavy boron-doping of Si or SiGe induces an increase of the growth rate which is slightly higher for Si than for SiGe (from 9.5 up to 18.5 nm min À1 for Si:B, and from 9.4 up to 16.0 nm min À1 for SiGe:B). Quite the opposite is found for phosphorus-doped Si or SiGe layers, with a growth rate which is dramatically reduced with high amounts of phosphine sent onto the growing surface, in agreement once again with Ref.…”

“…Ni or Pt), etc. Using SiGe instead of Si might help in incorporating a larger amount of electrically active dopants and reduce, for a given growth rate, the required growth temperature [4,10,12].…”

Reduced pressure–chemical vapor deposition of high Ge content Si1−xGex and high C content Si1−yCy layers for advanced metal oxide semiconductor transistors

“…550 1C) has different reasons whether we are talking of Si 1Àx Ge x or Si 1Ày C y . Adopting low growth temperatures enables, when dealing with the selective epitaxial growth of very high Ge content (25-50%) Si 1Àx Ge x layers inside the Si windows of SiO 2 -masked wafers, to get rid of any elastic strain relaxation through the formation of an undulating growth front [8,9]. Reducing the growth temperature as much as possible (while still keeping growth rates which are not insignificant) permits to have most of the incorporated C atoms in very high C content Si 1Ày C y layers (y41.5%, typically) occupying substitutional sites instead of electrically harmful interstitial sites [5,6].…”

Selective epitaxial growth of Si and SiGe for metal oxide semiconductor transistors

“…the slight modification (increase [18] or decrease [17]) of the SiGe growth rate and of the Ge concentration) when going over from a large area to a small area Si window in the patterned wafer. Reducing the growth temperature helps, when selectively growing high Ge concentration SiGe films inside the Si windows of patterned wafers, in minimizing the surface roughness [26] (elastic strain relaxation).…”