Selecting Microarchitecture Configuration of Processors for Internet of Things (IoT)

Abstract

The Internet of Things (IoT) makes use of ubiquitous internet connectivity to form a network of everyday physical objects for purposes of automation, remote data sensing and centralized management/control. IoT objects need to be embedded with processing capabilities to fulfill these services. The design of processing units for IoT objects is constrained by various stringent requirements, such as performance, power, thermal dissipation etc. In order to meet these diverse requirements, a multitude of processor design parameters need to be tuned accordingly. In this paper, we propose a temporally efficient design space exploration methodology which determines power and performance optimized microarchitecture configurations. We also discuss the possible combinations of these microarchitecture configurations to form an effective two-tiered heterogeneous processor for IoT applications. We evaluate our design space exploration methodology using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH2 benchmarks. The results show that our methodology determines microarchitecture configurations which are within 2.23%-3.69% of the configurations obtained from fully exhaustive exploration while only exploring 3%-5% of the design space. Our methodology achieves on average 24.16× speedup in design space exploration as compared to fully exhaustive exploration in finding power and performance optimized microarchitecture configurations for processors.Index Terms-Internet of Things (IoT), design space exploration, microarchitecture, tunable processor parameters, cycle-accurate simulator (ESESC), PARSEC and SPLASH2 benchmarksThe authors are with the

Towards Energy-Efficient Heterogeneous Multicore Architectures for Edge Computing

“…Our solution combines a high-performance core suitable for sequential execution, and several lightweight low power cores devoted to parallel execution. Prototypes of designed architectures have been implemented on FPGA and reported performance and power consumption figures were measured rather than estimated as in existing works [40], [41]. Further, a tailored and flexible multi-task execution model / API is proposed for efficiently leveraging the flexibility offered by the template in selecting at run-time target cores for processing.…”

“…The current paper deals with similar issues as in [40], [41]. It relies on a novel asymmetric single-ISA architecture built with cost-effective and very low power core technology.…”

“…In [40], authors tried to understand the interaction between execution characteristics of IoT applications (such as compute or memory intensity) and the architectural features of edge nodes (such as clock frequency, memory capacity) designed with ARM and Intel CPUs. In [41], authors described a design space exploration methodology that focuses on the combination of different CPU microarchitectures to design energy-efficient processors for IoT applications. In both studies, authors mainly focused on the impact of CPU frequencies and cache sizes on the performance and energy when executing the considered benchmarks.…”

Systematic Approach for State-of-the-Art Architectures and System-on-Chip Selection for Heterogeneous IoT Applications

“…The processor selection approach remained carried out using greedy search methods. The proposed processor configuration utilizes only 3% to 5% of the overall design space, significantly increasing the average speed up on processor design [28]. The work in [28] is significant towards the processor selection constraint.…”

“…The proposed processor configuration utilizes only 3% to 5% of the overall design space, significantly increasing the average speed up on processor design [28]. The work in [28] is significant towards the processor selection constraint. However, the greedy algorithms be unsuccessful to find the globally optimal solution for the reason that they do not consider all the data.…”