Towards Energy-Efficient Heterogeneous Multicore Architectures for Edge Computing

Machine learning algorithms are compute-and memory-intensive. Their execution at the edge on resourceconstrained embedded systems is challenging. Data quantization, i.e. data bit-width reduction, contributes to reducing de-facto the memory bandwidth requirement. In order to best exploit this bit-width reduction, a prevailing approach consists of tailored hardware accelerators. Another approach relies on generalpurpose compute units with Single Instruction Multiple Data (SIMD) support for reduced data bit-width precision, as in ARM Cortex-M [1] or RISC-V based RI5CY [2] processors. However, such processors only handle a few predefined bit-width ranges, e.g. 8-bit and 16-bit only for the ARM SIMD.This paper proposes a flexible architecture of Multiply-and-Accumulate (MAC) unit allowing asymmetric multiplication for operand sizes in powers of 2, up to 32 bits. The synthesis of this architecture in 28nm FD-SOI technology shows 10% and 25% reduction in area and dynamic power respectively, compared to the RI5CY MAC unit. From the energy-efficiency point of view, up to 50% improvements are achieved.

show abstract

“…Future work include the integration of the proposed MAC unit to typical low-power cores, e.g. RI5CY [2] or Cortus APS25 [21].…”

Section: Discussionmentioning

confidence: 99%

Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing

Devic

France-Pillois

Salles

et al. 2021

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Notably, in ARM Cortex A8 IoT CPU core, the unavailability of multicore and order of execution pipelined architecture operates with reduced power consumption and area. The multicore processors are more beneficial to deliver high performance for edge computing applications such as audiovideo processing and complex data acquisition systems [51].…”

Section: B Shared Heterogeneous Architecturementioning

confidence: 99%

Systematic Approach for State-of-the-Art Architectures and System-on-Chip Selection for Heterogeneous IoT Applications

et al. 2021

View full text Add to dashboard Cite

The Internet of Things (IoT) refers to a network of physical devices, which collects data and processes into a system without human intervention. In the commercialized market, IoT architectures are upgrading day by day to reduce data transmission costs, latency, and bandwidth usage for various application requirements. The extensively available IoT architectures and their specification resist the researchers to select a system-on-chip (SoC) for heterogeneous IoT applications. This paper seeks to comprehend the various IoT device specifications and their characteristics to support multiple applications. Moreover, microprocessor architectures and their components are detailed to facilitate developer knowledge in advanced methodology and technology. The various instructions set architectures (ISA) are implemented in a Zynq-7000 (xc7Zz20clg484-1) FPGA device to examine the feasibility of design space requirements for real-time hardware execution. To select specific system-on-chip (SoC) architecture for heterogeneous IoT applications, a genetic algorithm (GA) based optimization method is implemented in MATLAB. The proposed algorithm identifies the optimized SoC architecture concerning device parameters such as a clock, cache, RAM space, external storage, network support, etc. Further, the confusion matrix method evaluates the proposed algorithm's accuracy, which yields 84.62% accuracy. The outcome of SoCs attained through the GA are tested by analyzing their execution time and performance using various evaluation benchmarks. This article helps the researchers and field engineers to comprehend the microarchitecture device configurations and to identify the superior SoC for next-generation IoT practices.INDEX TERMS Internet of Things, Microprocessors, System-on-chip, Heterogeneous Architectures, and Edge Computing.

show abstract

“…In [14]- [17], only external scheduling is addressed. The cases of multicore are considered in [18]- [20] for the speed-up of the task execution. In [18], they inspect how the number of cores affects the system performance.…”

Section: Related Workmentioning

confidence: 99%

“…The cases of multicore are considered in [18]- [20] for the speed-up of the task execution. In [18], they inspect how the number of cores affects the system performance. Their scheduling allocates tasks to edge servers by weighing the availabilities of cores and tasks.…”

Section: Related Workmentioning

confidence: 99%

Task Scheduling With Multicore Edge Computing in Dense Small Cell Networks

Lai

Shieh²,

Chen

2021

IEEE Access

View full text Add to dashboard Cite

As a reaction and complement to cloud computing, edge computing is a computing paradigm designed for low-latency computing. Edge servers, deployed at the boundary of the Internet, bridge those distributed end devices and the centralized cloud server, forming a harmonic architecture with low latency and balanced loadings. Elaborated task scheduling, including task assignment and processor dispatching, is essential to the success of edge computing systems in dense small cell networks. Plenty of issues need to be considered, such as servers' computing power, storage capacity, loadings, bandwidth and tasks' sizes, delays, partitionability, etc. This study contributes to the task scheduling for multicore edge computing environments. We first show that this scheduling problem is an NP-hard problem. An efficient and effective heuristic is then proposed to tackle the problem. Our Multicore Task assignment for maximum Rewards (MAR) scheme differs from most previous schemes in jointly considering all three critical factors: namely task partitionability, multicore, and task properties. A task's priority is decided by its cost function, which takes into account the task's size, deadline, partitionability, cores' loadings, processing power, and so forth. First, tasks from end devices are assigned to edge servers considering servers' loadings and storage. Next, tasks are assigned to the cores of the selected server. Simulations compare the proposed scheme with First-Come-First-Serve (FCFS), Shortest Task First (STF), Delay Priority Scheduling (DPS), and Green Greedy Algorithm (GGA). Simulations demonstrate that the task completion ratio can be significantly increased, and the number of aborted tasks can be greatly reduced. Compared with FCFS (First-Come-First-Serve), STF (Shortest Task First), DPS (Delay Priority Scheduling), and GGA (Green Greedy Algorithm), the improvement in task completion ratio for hotspots is up to 26%, 25%, 22%, and 9%, respectively.INDEX TERMS Task scheduling, edge computing, multicore.

show abstract

Towards Energy-Efficient Heterogeneous Multicore Architectures for Edge Computing

Cited by 22 publications

References 45 publications

Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing

Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing

Systematic Approach for State-of-the-Art Architectures and System-on-Chip Selection for Heterogeneous IoT Applications

Task Scheduling With Multicore Edge Computing in Dense Small Cell Networks

Contact Info

Product

Resources

About