Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique

Abstract

A new Digital Pulse Width Modulator (DPWM) design for a Field Programmable Gate Array (FPGA) based systems is presented in this paper. The proposed architecture fully utilizes the Digital Clock Manager (DCM) resources available on new FPGA boards. The proposed Segmented DCM DPWM is a digital modulator architecture with low power that allows for high switching frequency operation. It relies on the power-optimized resources already existing on new FPGAs. The inherit phase shifting properties of the DCM blocks simplify the duty cycle generation. The architecture can be applied to achieve various number of bits for the DPWM resolution, and is implemented and verified experimentally on a Virtex4 FPGA board.

ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

“…The architectures can be easily implemented either on ASIC or FPGA. However, the high switching frequency and high DPWM resolution may result in impractically large clock frequency requirement and thus large power consumption [53,63], which turns out to be the disadvantage.…”

“…This eliminates any mismatched delay in the path of delay cell output to the reset terminal of the flip-flop. These architectures use clock frequency as a switching frequency unlike in that used in counter based architectures, this helps to decrease the power consumption at the expense of large area due to area consuming multiplexer [3,53,55,63]. The size of the multiplexer grows exponentially with the increase in the resolution bits ( ).…”

“…Classical methods provide many solutions but do not provide an adequate resolution. In this section new architectures for increasing the resolution of the DPWM by using advance resources of the FPGA and the hybrid architecture with software [46,53]. All of these architectures belong to the class of hybrid architectures.…”

“…Another architecture, which fully utilizes inherited phase shifting properties of the DCM blocks, simplifies the duty cycle generation capabilities as reported by Batarseh et.al. [46]. It is a hybrid approach, combining the linear countercomparator and the FPGA on-board DCM resources, offering reduced external clock frequency and thus, allowing high switching frequency operation.…”

“…It is a hybrid approach, combining the linear countercomparator and the FPGA on-board DCM resources, offering reduced external clock frequency and thus, allowing high switching frequency operation. Further reducing the power dissipation in the architecture, Batarseh et.al [53] introduced the window mask concept in the architecture of [46]. A very high resolution DPWM was proposed by Castro and Todorovich in 2010 [52] which took advantage of advanced clock management capability called the fine phase shifting of the clock.…”