Secondary Electron flash-a high performance, low power flash technology for 0.35 μm and below

Bude, J.; Mastrapasqua, M.; Pinto, M.R.; Gregor, R.W.; Kelley, P.J.; Kohler, R.A.; Leung, CW; Ma, Yutang; McPartland, Richard J.; Roy, Palash; Singh, Ranbir

doi:10.1109/iedm.1997.650381

Cited by 57 publications

(16 citation statements)

References 4 publications

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“…2 shows T P as a function of V D for different V B at a constant V CG . However, it should also be noted that programming using the secondary electrons is a self-limiting process, where the maximum V TH attainable is limited by V CG [6]. Fig.…”

Section: A Effect Of Substrate Bias On Program and Drain Disturbmentioning

confidence: 99%

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Using Soft Secondary Electron Programming to Reduce Drain Disturb in Floating-Gate NOR Flash EEPROMs

Kumar

Nair

Mahapatra

2006

IEEE Trans. Device Mater. Relib.

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Abstract-A novel concept of soft secondary electron programming (SSEP) is introduced and shown to be a promising programming scheme for scaled NOR flash electrically erasable programmable read-only memories. Although the mechanism is similar to that of the channel-initiated secondary electron (CHISEL) programming, SSEP uses an "optimum" substrate bias that results in a lower drain disturb compared with both channel hot electron (CHE) and conventional CHISEL programming schemes. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, as well as better program/disturb margin compared with conventional CHISEL programming at similar program speed or disturb time. The effect of repeated program/erase cycling using SSEP is compared against CHE and CHISEL cycling.Index Terms-Band-to-band tunneling, channel hot electron (CHE), channel-initiated secondary electron (CHISEL), cycling endurance, drain disturb, flash electrically erasable programmable read-only memory (EEPROM), secondary electrons.

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Section: A Effect Of Substrate Bias On Program and Drain Disturbmentioning

confidence: 99%

“…Compared with CHE, CHISEL offers faster program speed under equivalent power, lower power consumption under similar speed, better cycling endurance of V TH window, and lower degradation of program time T P [6], [9], [10], [16], [17]. CHISEL also leads to a selfconvergent programming, giving a better control over program V TH [4], [6], [11].…”

mentioning

confidence: 99%

Using Soft Secondary Electron Programming to Reduce Drain Disturb in Floating-Gate NOR Flash EEPROMs

Kumar

Nair

Mahapatra

2006

IEEE Trans. Device Mater. Relib.

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“…In CHISEL programming, holes generated out of impact ionization (II) by channel electrons get accelerated by large vertical field of drain-substrate junction (DSJ) (due to V B ) and cause further II. The generated secondary electrons gain energy in DSJ vertical field and get injected into FG, thereby enhancing programming efficiency [2][3][4][5]. From a programming perspective SSEP operates midway between CHE and CHISEL, and utilizes an optimum V B determined by drain disturb minimization (as explained later) rather than programming efficiency maximization (as historically is the case for CHISEL).…”

Section: Introductionmentioning

confidence: 99%

“…Compared to CHE, CHISEL offers faster program speed, lower power consumption, and much better cycling endurance [2][3][4][5], but results in a higher program drain disturb [6]. CHE drain disturb originates from sub-threshold channel leakage and worsens when L FG is scaled, and CHISEL drain disturb originates from band-to-band-tunneling (BTBT) at drain junction and worsens when S/D junction depth (X J ) is scaled [6].…”

Section: Introductionmentioning

confidence: 99%

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Soft secondary electron programming for floating gate NOR flash EEPROMs

Kumar

Nair

Mahapatra

Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005.

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A novel scheme called Soft Secondary Electron Programming (SSEP) is introduced and shown to be a promising programming mechanism for scaled NOR Flash EEPROMs. SSEP involves use of an "optimum" V B that results in a lower drain disturb compared to both Channel Hot Electron (CHE) and CHannel Initiated Secondary Electron (CHISEL) mechanisms. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, and better program/disturb margin compared to CHISEL at similar program speed or disturb time.

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Principles of Floating Gate Devices

Floating Gate Devices: Operation and Compact Modeling

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The floating gate device is the basic building block for many types of nonvolatile memories: Flash, EPROM and EEPROM. In a memory product, single FG devices have to be connected together and compacted to use the smaller possible area on silicon. Depending on applications, different architectures have been introduced and manufactured. Some allow parallel access (program and read of a randomly addressed cell) and are better suited for embedded applications, others allow serial access (read and program are performed by page, i.e. more cells at the same time) and are better suited for mass storage applications.In this Chapter we will illustrate the physical mechanisms involved in FG program and erase operations. We will investigate the effects of these mechanisms on the reliability of the single FG device. We will also show that when a single FG device is part of an array, many reliability issues can arise. All this information will be used to forecast scaling issues of the FG device.

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Secondary Electron flash-a high performance, low power flash technology for 0.35 μm and below

Abstract: This work presents recent results on Secondary Electron flash memory, and contrasts this approach to standard techniques for scaled, low power mass storage applications.

Cited by 57 publications

References 4 publications

Using Soft Secondary Electron Programming to Reduce Drain Disturb in Floating-Gate NOR Flash EEPROMs

Using Soft Secondary Electron Programming to Reduce Drain Disturb in Floating-Gate NOR Flash EEPROMs

Soft secondary electron programming for floating gate NOR flash EEPROMs

Principles of Floating Gate Devices

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