2022
DOI: 10.1109/access.2022.3167732
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Second-Order Arnoldi Reduction Using Weighted Gaussian Kernel

Abstract: Modeling and design of on-chip interconnect continue to be a fundamental roadblock for high-speed electronics. The continuous scaling of devices and on-chip interconnects generates self and mutual inductances, resulting in generating second-order dynamical systems. The model order reduction is an essential part of any modern computer-aided design tool for prefabrication verification in the design of on-chip components and interconnects. The existing second-order reduction methods use expensive matrix inversion… Show more

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Cited by 2 publications
(1 citation statement)
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“…ern design tools for the simulation of on-chip interconnect are numerically expensive and often lack passivity preserving approximation of on-chip systems [8], [9]. In recent decades, complex and large-scale Model Order Reduction (MOR) has been a subject of major interest [10], [11], [12], [13], [14].…”
Section: Introductionmentioning
confidence: 99%
“…ern design tools for the simulation of on-chip interconnect are numerically expensive and often lack passivity preserving approximation of on-chip systems [8], [9]. In recent decades, complex and large-scale Model Order Reduction (MOR) has been a subject of major interest [10], [11], [12], [13], [14].…”
Section: Introductionmentioning
confidence: 99%