Abstract:The continuous scaling of the on-chip devices and interconnects increases the complexity of the design space and becomes a crucial factor in the fabrication of modern integrated circuits. The ever decreasing of interconnect pitch along with process enhancement into the nanometer regime had shifted the paradigm from a device-dominated to an interconnect-dominated methodology. In the design methodology, Model Order Reduction (MOR) reduces the size of large-scale simulation of on-chip interconnect to speed up the… Show more
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