Seamless Integration of SER in Rewiring-Based Design Space Exploration

Almukhaizim, Sobeeh; Makris, Yiorgos; Yang, Yi; Veneris, Andreas

doi:10.1109/test.2006.297682

Cited by 28 publications

(32 citation statements)

References 29 publications

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“…Techniques that increase logic masking include triplemodular redundancy, partial logic replication [15], guided rewiring [1], and signature-based partial redundancy addition [11]. These techniques mask errors on state elements, but often adversely affect testability and generally involve significant area overhead.…”

Section: Techniques For Ser Mitigationmentioning

confidence: 99%

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Improving testability and soft-error resilience through retiming

Krishnaswamy

Markov

Hayes

2009

Proceedings of the 46th Annual Design Automation Conference

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State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing masking. Most prior methods of reducing the soft-error rate (SER) involve combinational redesign, which tends to add area and decrease testability, the latter a concern due to the prevalence of manufacturing defects. Our work explores the fundamental relations between the SER of sequential circuits and their testability in scan mode, and appears to be the first to improve both through retiming. Our retiming methodology relocates registers so that 1) registers become less observable with respect to primary outputs, thereby decreasing overall SER, and 2) combinational nodes become more observable with respect to registers (but not with respect to primary outputs), thereby increasing scantestability. We present experimental results which show an average decrease of 42% in the SER of latches, and an average improvement of 31% random-pattern testability.

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Section: Techniques For Ser Mitigationmentioning

confidence: 99%

“…1 Our retiming method utilizes the relationship between signal observability, soft-error propagation, and random-pattern testability. We derive linear programs (LPs) that relocate registers so as to minimize their sequential observability.…”

Section: Introductionmentioning

confidence: 99%

Improving testability and soft-error resilience through retiming

Krishnaswamy

Markov

Hayes

2009

Proceedings of the 46th Annual Design Automation Conference

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“…Almukhaizim et al [1] use rewiring to increase reliability. The authors of [9] guide a local transformation technique known as rewriting to replace 4-input cuts in a circuit with more reliable sub-circuits.…”

Section: Previous Workmentioning

confidence: 99%

“…The union of two intervals can result in two separate intervals if the respective intervals are disjoint, or one if the intervals overlap. In general, the latching window for a gate g is defined by a sequence of intervals ELW (g) [0], ELW (g) [1] . .…”

Section: Static Analysismentioning

confidence: 99%

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On the role of timing masking in reliable logic circuit design

Krishnaswamy

Markov

Hayes

2008

Proceedings of the 45th Annual Design Automation Conference

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Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking mechanisms: logic, timing and electrical. Most previous papers focus on logic and electrical masking. In this paper we develop static and statistical analysis techniques for timing masking that estimate the error-latching window of each gate. Our SER evaluation algorithms incorporating timing masking are orders of magnitude faster than comparable evaluators and can be used in synthesis and layout. We show that 62% of gates identified as error-critical using timing masking would not be identifiable by considering only logic masking. Furthermore, hardening the top 10% of errorcritical gates leads to a 43% reduction in the SER. We also propose a more subtle solution, gate-relocation for technologies where wire delay dominates gate delay. We decrease the error-latching window of each gate by relocating it in such a way that path lengths to primary outputs are equalized. Our results show a 14% improvement in SER with no area overhead.

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