On the role of timing masking in reliable logic circuit design

Abstract

Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking mechanisms: logic, timing and electrical. Most previous papers focus on logic and electrical masking. In this paper we develop static and statistical analysis techniques for timing masking that estimate the error-latching window of each gate. Our SER evaluation algorithms incorporating timing masking are orders of magnitude faster than comparable evaluators and can be used in synthesis and layout. We show that 62% of gates identified as error-critical using timing masking would not be identifiable by considering only logic masking. Furthermore, hardening the top 10% of errorcritical gates leads to a 43% reduction in the SER. We also propose a more subtle solution, gate-relocation for technologies where wire delay dominates gate delay. We decrease the error-latching window of each gate by relocating it in such a way that path lengths to primary outputs are equalized. Our results show a 14% improvement in SER with no area overhead.

Design, Analysis and Test of Logic Circuits Under Uncertainty

“…Solutions at the logic and transistor levels tend to be more general and do not depend on the function of the circuit. Our work indicates that fine-grained, accurate SER analysis at low levels is computationally feasible and decreases overhead [58,59,55]. Table 1.2 summarizes the fault-tolerance techniques and masking mechanisms discussed in this section.…”

“…The authors of SET do provide another vector-driven mode that computes SER vector-by-vector to account for input-pattern dependence. Our work aims to build SER analysis tools that are scalable and can be used early in the logic design phase [58,59,55]. Due to our emphasis on reliability-driven logic design, we focus on modeling logical masking both accurately and efficiently.…”

A practical metric for soft error vulnerability analysis of combinational circuits

“…A similar technique to estimate timing masking factor was presented in [38]. Also in [39], there is a static approach for computing the timing masking factor by retracing the propagation back from latching flip-flops based on a simple static timing analysis. However, the proposed approach completely ignores electrical masking effect and uses logic simulation to estimate logic masking effect which imposes a tradeoff between estimation accuracy and its runtime.…”

“…After calculating TCS for the nodes connected to PO's, the PVW set of the fan-in gates of the circuit nodes (i.e. the gates which are connected to the gate input) are computed using the proposed computation model in Table 2 (36)(37)(38)(39). This cycle of estimation procedure of TCS and PVW computation is repeated level by level until all gates in all levels are visited.…”

Design as you see FIT: System-level soft error analysis of sequential circuits

“…Depending upon the input vector applied to the circuit when the strike occurs, three masking factors can prevent the glitch from causing an upset in state [11] Timing masking of a single path can be resolved using an analytical approximation instead of exhaustive simulation [19,16,20]. The work of Krishnaswamy et al [10] and of Asadi and Tahoori [1] apply accurate unified analysis of timing and logical masking including multiple sensitized paths, but neglect electrical masking entirely.…”