Improving testability and soft-error resilience through retiming

Abstract

State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing masking. Most prior methods of reducing the soft-error rate (SER) involve combinational redesign, which tends to add area and decrease testability, the latter a concern due to the prevalence of manufacturing defects. Our work explores the fundamental relations between the SER of sequential circuits and their testability in scan mode, and appears to be the first to improve both through retiming. Our retiming methodology relocates registers so that 1) registers become less observable with respect to primary outputs, thereby decreasing overall SER, and 2) combinational nodes become more observable with respect to registers (but not with respect to primary outputs), thereby increasing scantestability. We present experimental results which show an average decrease of 42% in the SER of latches, and an average improvement of 31% random-pattern testability.

Improving hardware Trojan detection by retiming

“…Extra FFs can be inserted if their cost is acceptable. Other design goals such as low power and testability can also be focused during retiming [15,16]. Retiming was introduced by Leiserson and Saxe in [17].…”

“…Vertices which need FF insertion must propagate their requests to all their fanout paths. the CR values (lines [13][14][15][16]. As extra FFs are inserted at the outputs, the FF shifting is performed in reverse topological order (line 13).…”

“…When the vertex is selected, the corresponding edge is removed from the cycle. The vertex connected to the other side of the edge is connected to one extra zero-weight PI or PO (lines [15][16][17][18][19][20][21][22][23][24][25][26]. Weights are preserved for all edges.…”

In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults

“…[35] uses retiming technology to harden the circuit for SEU as well as improve testability. However, because of the inherent difference between SEU and SET-induced faults, specific techniques for SET mitigation are needed.…”

RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications

“…In fact, the criticality of a logic gate returned by RALF is equal to the fault detection probability. In general, fault-tolerant logic synthesis tends to increase logic masking to prevent the propagation of faults [1], [5], which inevitably lowers the testability of a circuit [12]. By using RALF for post-synthesis RPR fault detection, BIST or other testability enhancement techniques can be specifically applied to gates with RPR faults.…”