2011
DOI: 10.1109/tcsi.2010.2094370
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In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults

Abstract: Abstract-For anti-fuse or flash-memory-based field-programmable gate arrays (FPGAs), single-event transient (SET)-induced faults are significantly more pronounced than single-event upsets (SEUs). While most existing work studies SEU, this paper proposes a retiming algorithm for mitigating variational SETs (i.e., SETs with different durations and strengths). Considering the reshaping effect of an SET pulse caused by broadening and attenuation during its propagation, SET-aware retiming (SaR) redistributes combin… Show more

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Cited by 10 publications
(4 citation statements)
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References 32 publications
(17 reference statements)
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“…The pulse broadening combined with the higher work frequencies and the higher technology scaling of SRAM-based FPGAs make SEUs induced by SETs sampling a common source of errors for them, more than in Flash-based FPGAs [13]. In order to assert how much a memory element can be affected by soft errors caused by SETs, the value of the PIPB introduced by the combinational logic located between the node where the pulse is generated, and the input of the memory element is fundamental [14].…”
Section: Background and Related Work A Propagation Induced Pulse Broadening And Errorsmentioning
confidence: 99%
“…The pulse broadening combined with the higher work frequencies and the higher technology scaling of SRAM-based FPGAs make SEUs induced by SETs sampling a common source of errors for them, more than in Flash-based FPGAs [13]. In order to assert how much a memory element can be affected by soft errors caused by SETs, the value of the PIPB introduced by the combinational logic located between the node where the pulse is generated, and the input of the memory element is fundamental [14].…”
Section: Background and Related Work A Propagation Induced Pulse Broadening And Errorsmentioning
confidence: 99%
“…A preliminary place and route algorithm developed for this specific purpose has been proposed in [68], while a placement re-timing algorithm has been proposed in [82]. However, an accurate radiation experiment evaluation of this approach [69] showed that it is only capable to partially reduce the overall SET sensitivity of a circuit, while most of the transient errors are bypassing the filtering optimizations.…”
Section: Previous Analysis and Mitigation Techniques For Sees Onmentioning
confidence: 99%
“…Single event transients (SETs), voltage disturbances generated when particles strike sensitive nodes [1], may propagate through the logic and eventually be latched, leading to behavioural errors of affected circuits [2]. As technology shrinks and operating frequencies increase, SETs are an ever-increasing issue for integrated circuits (ICs) adopted in safety-critical applications [3,4,5,6].…”
Section: Introductionmentioning
confidence: 99%