SDF

Ouyang, Jian; Lin, Shiding; Jiang, Song; Hou, Zhenyu; Wang, Yong; Wang, Yuanzheng

doi:10.1145/2541940.2541959

Cited by 131 publications

(15 citation statements)

References 9 publications

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“…In VBP-FAST, a VBlock does not occupy all the channels of SSD because there are many channels in a SSD. Such as in a Baidu SDF storage system, it has 44 channels in a SSD [Ouyang et al 2014]. Suppose that a VBlock occupies four channels: when a VBlock is doing Garbage Collection (GC) the other VBlocks can keep working in different channels.…”

Section: Architecture Of Vbp-fastmentioning

confidence: 99%

“…In order to reduce the effect GC, VBP-FAST (1) starts the GC process when the system is idle and (2) isolates GC in that, when a VBlock is doing garbage collection, the VBlocks that are not on the same channel as the VBlock in GC can keep working normally to exploit the channel-level parallelism in SSD. For example, there are 44 channels in each SSD of the Baidu SDF storage system [Ouyang et al 2014]. In a VBlock, a Big-page occupies at most 16 channels (i.e., 16 channels, a chip has two dies, a die has two planes, and a block has 64 pages).…”

Section: Switch and Partial Mergementioning

confidence: 99%

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Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks

Wang

Jiang

et al. 2014

ACM Trans. Archit. Code Optim.

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Compared with either block or page-mapping Flash Translation Layer (FTL), hybrid-mapping FTL for flash Solid State Disks (SSDs), such as Fully Associative Section Translation (FAST), has relatively high space efficiency because of its smaller mapping table than the latter and higher flexibility than the former. As a result, hybrid-mapping FTL has become the most commonly used scheme in SSDs. But the hybrid-mapping FTL incurs a large number of costly full-merge operations. Thus, a critical challenge to hybrid-mapping FTL is how to reduce the cost of full-merge operations and improve partial merge operations and switch operations. In this article, we propose a novel FTL scheme, called Virtual Block-based Parallel FAST (VBP-FAST), that divides flash area into Virtual Blocks (VBlocks) and Physical Blocks (PBlocks) where VBlocks are used to fully exploit channel-level, die-level, and plane-level parallelism of flash. Leveraging these three levels of parallelism, the cost of full merge in VBP-FAST is significantly reduced from that of FAST. In the meantime, VBP-FAST uses PBlocks to retain the advantages of partial merge and switch operations. Our extensive trace-driven simulation results show that VBP-FAST speeds up FAST by a factor of 5.3-8.4 for random workloads and of 1.7 for sequential workloads with channel-level, die-level, and plane-level parallelism of 8, 2, and 2 (i.e., eight channels, two dies, and two planes). , 2014. Improving hybrid FTL by fully exploiting internal SSD parallelism with virtual blocks. ACM Trans. Architec. Code

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Section: Architecture Of Vbp-fastmentioning

confidence: 99%

Section: Switch and Partial Mergementioning

confidence: 99%

Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks

Wang

Jiang

et al. 2014

ACM Trans. Archit. Code Optim.

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“…One popular example is Solid State Disks (SSD) that feature the advent of Multi-Level Cell (MLC) NAND flash memories to store a large amount of data in flash [Ouyang et al 2014]. However, with flash memory storage capacity roughly doubling every 18 months, designers face challenging performance and reliability problems [Micheloni et al 2010;Mielke et al 2008;Lee et al 2003;Bez et al 2003;Irom and Nguyen 2007].…”

Section: Introductionmentioning

confidence: 99%

“…New mobile usage models in today's complex embedded systems require the execution of multiple use cases on the same device and adaptation to the often nonpredictive behaviors of today's complex applications [Henkel et al 2011]. They require seamless integration of safety/time-critical functionalities with noncritical functionalities, with each one demanding different requirements from the storage system [Sampson et al 2013]. Moreover, NAND flash reliability is not constant; it changes over the device lifetime.…”

Section: Introductionmentioning

confidence: 99%

“…Concurrently with these solutions, several researchers focused on the optimization of the flash write algorithms [Liu et al 2012] to guarantee a performance-reliability tradeoff and on the use of adaptive ECC schemes to trade off storage space and performance for higher error correction capability [Chen et al 2009;Fabiano et al 2013]. Some studies also investigated how mechanisms that enable applications to store data approximately also enable improved performance whenever high-precision storage is not required [Sampson et al 2013]. However, a clear analysis of the benefits of combining optimized write algorithms with runtime-adaptable ECC schemes is still missing in the literature, thus preventing a clear understanding of the benefits an MLC NAND flash controller would achieve by implementing this higher level of configurability.…”

Section: Introductionmentioning

confidence: 99%

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Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Bertozzi

Carlo

Galfano

et al. 2015

ACM Trans. Embed. Comput. Syst.

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NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in non-volatile memories (NVMs), such as NAND flash memories, reliability and performance become a serious concern for systems’ designer. Designing NAND flash based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for run-time reconfigurability, adaptivity, and resource optimization in nowadays computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated trade-off point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reliability and power consumption acting on several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect the combined tuning of these parameters have on the full NVM sub-system. This paper performs a comprehensive quantitative analysis of the benefits provided by the run-time reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with run-time adaptation of the ECC correction capability. The full nonvolatile memory (NVM) sub-system is taken into account, starting from the characterization of the low level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide the readers a clear figure of the benefit this combined adaptation would provide at the system level

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Simulations of RRAM-Based SSDs

Zuolo

Zambelli

Micheloni

et al. 2017

Solid-State-Drives (SSDs) Modeling

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The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their fields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and sub-system technology. The series forms a bridge between physics and engineering, therefore the volumes will appeal to practicing engineers as well as research scientists.

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SDF

Cited by 131 publications

References 9 publications

Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks

Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Simulations of RRAM-Based SSDs

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