Scientific Application Acceleration with Reconfigurable Functional Units

The next generation radar systems have high performance demands on the signal processing chain. Among these are advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Massively Parallel Processor Arrays (MPPAs) are gaining attention to cope with the computational requirements of complex radar signal processing by exploiting the massive parallelism inherent in the algorithms in an energy efficient manner.In this paper, we evaluate two such massively parallel architectures, namely, Ambric and Epiphany, by implementing a significantly large case study of autofocus criterion calculation, which is a key component in future synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance, energy efficiency, and programmability.

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A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

Rousseau

Manet

Loiselle

et al. 2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.

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Scientific Application Acceleration with Reconfigurable Functional Units

Cited by 33 publications

References 21 publications

Operating System Support for Reconfigurable Computing

Operating System Support for Reconfigurable Computing

Real-time radar signal processing on Massively Parallel Processor Arrays

A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

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