Scaling of TG-FinFETs: 3-D Monte Carlo Simulations in the Ballistic and Quasi-Ballistic Regimes

Elthakeb, Ahmed T.; Elhamid, Hamdy Abd; Ismail, Yehea

doi:10.1109/ted.2015.2420580

Cited by 14 publications

(2 citation statements)

References 30 publications

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“…For FinFET, the body thickness T Fin should be approximately half of the gate length L G to provide better control of short channel effects. When the L G /T FIN ratio is smaller than 1.5, the drain induced barrier lowering, subthreshold swing, and leakage current are increased sensibly [2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Boukortt¹,

Hadri²,

Caddemi³

et al. 2016

Transactions on Electrical and Electronic Materials

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In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator ATLAS™ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/ off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

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Section: Introductionmentioning

confidence: 99%

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Boukortt¹,

Hadri²,

Caddemi³

et al. 2016

Transactions on Electrical and Electronic Materials

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“…The study of the advanced FinFET technology is a current topic of research for all the production companies, like TSMC, Intel, and Samsung, which are in the race to get a high performance of microprocessors beyond the barrier of 14 nm. Among all, FinFET is one of the most attractive devices for implementing nanoscale CMOS technology node applications, since this type of transistor provides a better scalability option due to its excellent immunity to short channel effects (SCEs) [1][2][3][4][5][6]. For the FinFET, the body thickness (T Fin ) should be approximately half of the gate length (L G ) to provide better control of short channel effects (SCEs).…”

Section: Introductionmentioning

confidence: 99%

Simulation of a Nanoscale SOI TG n-FinFET

Boukortt¹,

Hadri²,

Caddemi³

2016

IJCA

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The objective of this work is to study the electrical characteristics of a nanoscale SOI Tri-Gate n-channel fin field-effect transistor (FinFET) structure with 8 nm gate length using Semiconductor TCAD tools. ATLAS™ tools are computer programs which allow for the creation, fabrication, and simulation of semiconductor devices in three dimensions with different models under consideration. The drain current, transconductance, threshold voltage, subthreshold slope, leakage current, drain induced barrier lowering, and I On /I Off current ratio are analyzed in the various biasing configuration. In addition, FinFET device with a high value of gate dielectric constant exhibits much better performance compared to the Si 3 N 4 dielectric material, which is desirable for high performance low-power/low-voltage applications. It is found that increasing the high-k value was beneficial in reducing the subthreshold slope, DIBL, and leakage current. General TermsIntegrated Circuit, VLSI, FinFET Device Modeling.

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