Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

Abstract

In this paper, Tri-Gate Nanowire (TGNW) FETs with high-κ/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long-and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model

“…The same trend emerges for both types of device (Trigate and FinFET) with reducing the channel width W top : a decrease of mobility with decreasing W top for NMOS devices and an increase of mobility for PMOS devices. This behaviour is in qualitative agreement with the mobility model of separated conduction surfaces, in which the sidewalls exhibit a carrier mobility specific to (110)-inversion surfaces [24], [25]. As W top decreases, the carrier mobility tends to be equal to the limiting mobility of (110)-sidewall μ side .…”

A quantum device driven by an on-chip CMOS ring oscillator

“…The nanowire is connected to the outside of the cryostat by 4 pads (in black): two for the Source and Drain and two others for the DC biases to be applied on the top gates of the SET. From LETI, we use the so-called Trigate Silicon-On-Insulator technology, which allows to design side-by-side classical CMOS circuits based on wide channel MOSFETs and nanowires with a very small cross-section down to 10×10 nm [4], [5]. To obtain these aggressive dimensions, the actual fabrication process uses deep-UV lithography and resist trimming, hence it is not possible to obtain a very small spacing between 2 gates in Fig.…”

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

“…Multiple gate MOSFETs have attracted the interest of semiconductor industry due to strong immunity against short channel effects and great scalability because of improved electrostatic coupling [1]- [3]. Ωgate and GAA MOSFETs with nanoscale cross-section, also denominated as nanowires, turned into candidates for future technological nodes due to their performance [2], [4]. Such devices are fabricated with close dimensions for both silicon thickness (HFIN) and fin width (WFIN), around 10nm.…”