Scaling Analysis of Multilevel Interconnect Temperatures for High-Performance ICs

In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

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“…40 This is referred to as the chip junction temperature (T J ), which is always higher than the package temperature, related by Equation (4).…”

Section: Methodsmentioning

confidence: 99%

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

et al. 2015

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“…However, the average thermal conductance of the metal-dielectric layer is quite low when compared to the bottom heat conduction path (through heat spreader and heat sink). Moreover, the heat conduction of the metaldielectric layer is even less in deep sub-micron technologies due to the low thermal conductance of the low-κ materials [27]. Therefore, the upper part of the chip is assumed to be thermally insulator.…”

Section: Self-heating Analysismentioning

confidence: 99%

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Baltacı

Leblebici

2017

Integration

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A B S T R A C TThermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40 nm node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations and hotspot locations are studied. The influence of local power density on peak temperature is examined. It is shown that high power density devices have significant influence on peak temperature in FDSOI. It is found that some group of devices that perform the same function are the most prominent heat generators. A modification on the design of these devices is proposed which decreases the hotspot temperatures significantly.

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“…path of electrons (~40 nm in Cu at room temperature) undergo resistance increase rapidly. This is due to the combined effects of enhanced grain boundary scattering, surface scattering and the presence of a highly resistive diffusion barrier layer surrounding the copper line [3,4]. Moreover, at nano-scale dimensions, the increase of Cu interconnect resistivity, in addition to the increasing current density (J), results in higher self-heating of interconnects.…”

Section: Introductionmentioning

confidence: 99%

“…Vias and interconnects have a thermal conductivity in the range of K th, Cu =385 W/mK. Nevertheless, thermal conductivity worsens when the back-end metal temperature (T m ) rises above the junction temperature [3]. Elevated temperatures along with scaling introduce reliability concerns on Cu lines with low-K dielectric also known as time dependent dielectric breakdown (TDDB).…”

Section: Introductionmentioning

confidence: 99%

“…Elevated temperatures along with scaling introduce reliability concerns on Cu lines with low-K dielectric also known as time dependent dielectric breakdown (TDDB). All these factors adversely affect electromigration (EM) lifetime of Cu interconnects which depends quadratically on J and exponentially on T m [3]. ITRS [2] reports that current density limits for copper will be exceeded by 2017.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

Todri‐Sanial

Ramos

Okuno

et al. 2017

IEEE Circuits Syst. Mag.

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Scaling Analysis of Multilevel Interconnect Temperatures for High-Performance ICs

Cited by 179 publications

References 34 publications

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

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