Scalable Compact Circuit Model for Differential Spiral Transformers in CMOS RFICs

Gao, Wei; Jiao, Chao; Liu, Tao

doi:10.1109/ted.2006.880230

Cited by 33 publications

(33 citation statements)

References 22 publications

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“…This double goal was accomplished by splitting the inductor into two equal parts L T /2 and by inserting a parallel RC network in the branch: at the LO frequency, the capacitor C L acts as a short circuit across the resistor R L and a high-Q inductor is obtained, while at low frequency, where the inductor impedance is negligible, R L provides transimpedance gain while the capacitor C L sets the -3 dB bandwidth of the receiver. To keep the layout compact, the two inductors L T /2 of each cell are realized as a single interleaved symmetrical transformer, without any area penalty, and exploiting the inductance boost given by the mutual coupling between the coils [11].…”

Section: Self-oscillating Mixer and Lc Tankmentioning

confidence: 99%

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

Camponeschi

Bevilacqua

Andreani

2010

Analog Integr Circ Sig Process

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In this work a 2.2 GHz quadrature receiver front-end suitable for low-power applications is presented. The low-noise amplifier, the mixer and the voltage-controlled oscillator are merged into a single stage, making the circuit capable of extreme current reuse while keeping it still functional at low supply voltage. A careful linear timevariant analysis is proven to be necessary to accurately predict the conversion gain and the bandwidth of the downconverter. A prototype, implemented in a 90 nm CMOS technology, validates the theoretical analysis, showing 27 dB of downconversion gain over a 14 MHz base-band bandwidth; the noise figure is 13 dB with a flicker corner frequency of 200 kHz; the input-referred 1 dB compression point is -23.7 dBm. The circuit draws only 1.3 mA from a 1.0 V supply.

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Section: Self-oscillating Mixer and Lc Tankmentioning

confidence: 99%

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

Camponeschi

Bevilacqua

Andreani

2010

Analog Integr Circ Sig Process

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“…However, the use of separate metal planes consequences in an asymmetry between the primary and secondary coils caused by the diverse thickness and metal characteristics of the planes. This layout is suitable for small frequency action as big capacitance between coils due to the overlap results in a low SRF (self resonating frequencies) [8]. An on-chip transformer model is needed for chip technologies.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Structure Optimization of Tapped Transformer

Namoune¹,

Hamid²,

Taleb

2017

IJECE

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In this paper, a simplified circuit model of the tapped transformer structure has been presented to extract the Geometric and technology parameters and offer better physical understanding. Moreover, the structure of planar transformer has been optimized by using changing the width and space of the primary coil, so as to enlarge the quality factor Q and high coupling coefficient K. To verify the results obtained by using these models, we have compared them with the results obtained by employing the MATLAB simulator. Very good agreement has been recorded for the effective primary inductance value, whereas the effective primary quality factor value has shown a somewhat larger deviation than the inductance.

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“…Many research works have been done on the modeling of on-chip transformers with different shapes and layouts [4][5][6][7][8][9][10][11]. For example, Mohan et al [4] has presented two analytical transformer models for both tapped and stacked geometries.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, a polygon is used because it is the next closest shape to the circular and the performance, at the meantime, is not compromised. A scalable model for the octagonalshaped interleaved transformers has been presented in [6]. A set of analytical formulas were developed to calculate the values of circuit elements based on the process parameters and transformer layout.…”

Section: Introductionmentioning

confidence: 99%

“…A set of analytical formulas were developed to calculate the values of circuit elements based on the process parameters and transformer layout. However, since all four ports of differential transformers in [6] are located on the same side, it will be very difficult to carry out on-wafer measurements. Typical G-S-G (Ground-Signal-Ground) or G-S-S-G (Ground-Signal-Signal-Ground) pad configuration will not work.…”

Section: Introductionmentioning

confidence: 99%

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Characterization, design and modeling of on-chip interleaved transformers in CMOS RFICs

Zhao

Yeo

Anh

et al. 2010

Analog Integr Circ Sig Process

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This paper discusses the impacts of key geometrical parameters on the performance of interleaved transformers in CMOS radio frequency integrated circuits (RFICs). It also presents a compact circuit model for the transformer based on the ''2-p'' model of on-chip spiral inductors. All the RLC circuit elements can be calculated from the transformer's geometrical and process parameters. Verification with accurately calibrated electromagnetic (EM) simulation data demonstrates accurate performance prediction and good scalability for a wide range of transformers' layout.

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Scalable Compact Circuit Model for Differential Spiral Transformers in CMOS RFICs

Cited by 33 publications

References 22 publications

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

Modeling and Structure Optimization of Tapped Transformer

Characterization, design and modeling of on-chip interleaved transformers in CMOS RFICs

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