Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs

Dorrance, Richard; Ren, Fengbo; Toriyama, Yuta; Hafez, Amr Amin; Yang, Chih-Kong Ken; Marković, Dejan

doi:10.1109/ted.2011.2182053

Cited by 71 publications

(25 citation statements)

References 33 publications

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“…1(b)), which have lower switching current densities. In circuit applications, both types of devices are similarly deployed, but they differ in attributes such as volume, aspect ratio, switching current, and scalability in future technologies [5], [7].…”

mentioning

confidence: 99%

Improving STT-MRAM density through multibit error correction

Bel

Kim

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-STT-MRAMs are prone to data corruption due to inadvertent bit flips. Traditional methods enhance robustness at the cost of area/energy by using larger cell sizes to improve the thermal stability of the MTJ cells. This paper employs multibit error correction with DRAM-style refreshing to mitigate errors and provides a methodology for determining the optimal level of correction. A detailed analysis demonstrates that the reduction in nonvolatility requirements afforded by strong error correction translates to significantly lower area for the memory array compared to simpler ECC schemes, even when accounting for the increased overhead of error correction.

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mentioning

confidence: 99%

Improving STT-MRAM density through multibit error correction

Bel

Kim

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…6 shows the sense error rate P SE in five process corners under MTJ resistance variation. Both of standard deviations R P =R P and T MR=T MR [T MR ¼ ðR AP À R P Þ=R P ] are set 5%, that are derived from measurement results [15]. Two capital letters such as 'TT' denote process corner of an NMOS transistor and that of a PMOS transistor (the letters F, T, S, correspond to fast, typical, slow, respectively).…”

Section: Evaluationsmentioning

confidence: 99%

“…The effect of MTJ resistance variation on sense error rate (P SE ). Both the standard deviations R P =R P and T MR=T MR [T MR ¼ ðR AP À R P Þ=R P ] are set 5% [15].…”

Section: Evaluationsmentioning

confidence: 99%

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Suzuki

Sakimura

Natsui

et al. 2014

IEICE Electron. Express

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A nonvolatile flip-flop (NV-FF) is proposed for a zerostandby-power LSI using a domain-wall motion (DWM) device. Since the write current path is separated from the read current path in the DWM device, two nonvolatile memory function blocks, a write driver for storing temporal data into the DWM device, and a sense amplifier for recalling the stored data from the DWM device can be optimized independently. Moreover, the use of a nonvolatile storage cell with a DWM-device-based single-ended structure makes it possible to implement both of these functions as two CMOS inverters, which makes it possible to merge them into a CMOS delay flip-flop (D-FF) core. Since the nonvolatile storage cell is electrically separated from the D-FF core during the normal operation, there is no performance degradation. In fact, the area and the power-delay product of the proposed NV-FF are minimized compared to those of the previous works.

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“…Also, there are several recent work on statistical parametric yield estimation for both timing and leakage power [Dorrance et al 2012]. Statistical timing analysis considering path correlation has been studied in Orshansky and Bandyopadhyay [2004], Le et al [2004], Zhan et al [2005], and Zhang et al [2005].…”

Section: Introductionmentioning

confidence: 99%

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

Cheng

Gong

et al. 2012

ACM Trans. Reconfigurable Technol. Syst.

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Process variation in nanometer technology is becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, we first develop closed-form models of chip-level FPGA leakage and timing variations. Experiments show that the mean and standard deviation computed by our models are within 3% from those computed by Monte Carlo simulation. We also observe that the leakage and timing variations can be up to 3X and 1.9X, respectively. We then derive analytical yield models considering both leakage and timing variations, and use such models to evaluate the performance of FPGA device and architecture considering process variations. Compared to the baseline, which uses the VPR architecture and device setup based on the ITRS roadmap, device and architecture tuning improves leakage yield by 10.4%, timing yield by 5.7%, and leakage and timing combined yield by 9.4%. We also observe that LUT size of 4 gives the highest leakage yield, LUT size of 7 gives the highest timing yield, but LUT size of 5 achieves the maximum leakage and timing combined yield. To the best of our knowledge, this is the first in-depth study on FPGA architecture and device coevaluation considering process variation.

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Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs

Cited by 71 publications

References 33 publications

Improving STT-MRAM density through multibit error correction

Improving STT-MRAM density through multibit error correction

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

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