SAT-Based Methods for Sequential Hardware Equivalence Verification without Synchronization

A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits Without Known Reset States

“…However, as our notion of equivalence is easier to compute than alignability, it is likely to be easier to compute than safe replacibility for the reasons outlined in [4]. Moreover, as top-level alignability implies nonempty ESP, and safe replacement for weakly synchronizable designs implies alignability [3], we can show at least as many weakly synchronizable designs equivalent as safe replacement checking. Finally, combinational equivalence is compositional with our notion of equivalence.…”

“…However, D1 was easy enough that pure sequential checking took less time than running our combination method, and our method was about 18X faster than a pure sequential analysis in the case of D3. We also tried our implementation of the SAT-based alignability checking from [3] for the 10 harder designs, but we could not solve any of them within 24 hours.…”

Reference model based RTL verification: an integrated approach

“…The implementation outlined in this paper uses a sequential equivalence checker (with dual rail modeling) similar to the one described in [10], with satisfiability [13], and a rich specification logic that is LTL based. Like many sequential FEV predecessors [14], the checker exploits the symmetry between the two models to simplify the verification task.…”

“…Most verification approaches are fairly poor in integrating the benefits from a smaller initial state space with the actual verification effort. In order to remedy this, A class of techniques at Intel [9,10] attempts to decouple the initialization process from the actual verification flow. The environmental assumptions originally formulated in temporal logic have to be restated in a form amenable to the initialization tools.…”

Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints

“…The reported run times were measured on a 2.4GHz Linux machine with 2GB memory. We use SAT-based algorithms similar to those reported in [RH02,KH03,KRSH04] in the alignability and 3-valued safe replaceability checks. We do not have a safe replaceability verification algorithm in Seqver, and cannot report corresponding experimental data.…”