A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits Without Known Reset States

Moon, In-Ho; Bjesse, Per; Pixley, Carl

doi:10.1109/date.2007.364453

Cited by 5 publications

(14 citation statements)

References 12 publications

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“…The beauty of the weak alignability approach is that the compositionality works with combinational equivalence checking and the verification can be performed on an abstraction/refinement scheme. However, one problem in the weak alignability is that the compositionality cannot be efficiently applied to designs that are retimed globally [12]. This is because the equivalence on retimed sub-blocks is broken while the design equivalence is preserved.…”

Section: Introductionmentioning

confidence: 94%

“…that often have different numbers of registers. Even though there have been many publications on sequential equivalence checking as in [13,5,20,18,19], the industry has started to use sequential equivalence checking only recently with practical approaches handling fairly large designs [7,8,1,12]. Baumgartner et al proposed sequential equivalence checking through a series of various transformations with a given reset state.…”

Section: Introductionmentioning

confidence: 98%

“…The necessary conditions computed are justified on their parent blocks by temporal equivalence [17]. Sequential equivalence checking on each modified block is performed by the weak alignability as in [12]. However, this verification can be done by any existing sequential equivalence checking approach.…”

Section: Introductionmentioning

confidence: 99%

“…Baumgartner et al proposed sequential equivalence checking through a series of various transformations with a given reset state. Another practical method is a compositional approach on sequential equivalence checking, called weak alignability [7,8,12]. The original alignability was introduced by Pixley as a good notion of sequential equivalence without a known reset state [13].…”

Section: Introductionmentioning

confidence: 99%

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Compositional verification of retiming and sequential optimizations

Moon

2008

Proceedings of the 45th Annual Design Automation Conference

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Once a design is both retimed and sequentially optimized, sequential equivalence verification becomes very hard since retiming breaks the equivalence of the retimed sub-blocks although the design equivalence is preserved.This paper presents a novel compositional algorithm to verify sequential equivalence of large designs that are not only retimed but also optimized sequentially and combinationally. With a new notion of conditional equivalence in the presence of retiming, the proposed compositional algorithm performs hierarchical verification by checking whether each sub-block is conditionally equivalent, then checking whether the conditions are justified on their parent block by temporal equivalence. This is the first compositional algorithm handling both retiming and sequential optimizations hierarchically. The proposed approach is completely automatic and orthogonal to any existing sequential equivalence checker. The experimental results show that the proposed algorithm can handle large industrial designs that cannot be verified by the existing methods on sequential equivalence checking.

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Section: Introductionmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Compositional verification of retiming and sequential optimizations

Moon

2008

Proceedings of the 45th Annual Design Automation Conference

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“…Baumgartner et al [5] discuss an approach for invariant generation to address the conditional equivalence checking problem for optimizations including clock gating and power gating. Moon et al [18] propose equivalence checking techniques that exploit well-partitioned circuit structures.…”

Section: Related Workmentioning

confidence: 99%

Handling design and implementation optimizations in equivalence checking for behavioral synthesis

Yang

Hao

Ray

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such equivalence checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate equivalence checking for behavioral synthesis: (1) operation gating, and (2) global variables. We develop a sequential equivalence checking (SEC) framework to compare ESL designs with RTL in the presence of these optimizations. Our approach can handle designs with more than 32K LoC RTL synthesized from practical ESL designs. Furthermore, our evaluation found a bug in a commercial tool, underlining both the importance of SEC and the effectiveness of our approach.

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