SAQP and EUV block patterning of BEOL metal layers on IMEC's iN7 platform

Bekaert, Joost; Lorenzo, Paolo Di; Mao, Ming; Decoster, Stefan; Larivière, S.; Franke, Joern-Holger; Carballo, V.M. Blanco; Kotowska, Bogumila Kutrzeba; Lazzarino, Frédéric; Gallagher, Emily; Hendrickx, Eric; Leray, Philippe; Kim, R. Ryoung-han; McIntyre, Greg; Colsters, Paul; Wittebrood, Friso; Dijk, Joep van; Maslow, Mark John; Timoshkov, Vadim; Kiers, Ton

doi:10.1117/12.2258004

Cited by 5 publications

(3 citation statements)

References 2 publications

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“…Metal process will continue to adopt selfaligned litho-etch-litho-etch (LELE) process with EUV lithography due to the needs for good overlay ( ≤ 2.5 nm) under ever-tightened design rules (CD~15-16 nm) [5,6] . Figure 9 is the process flow schematics.…”

Section: Metal Process Approach Discussionmentioning

confidence: 99%

A Study of 2D Assist Feature Placement

Zhu¹,

Ma²,

Shen³

et al. 2019

Journal of Microelectronic Manufacturing

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5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries. In a typical 5 nm logic process, the Fin pitch is 22~27 nm, the contact-poly pitch (CPP) is 48~55 nm, and the minimum metal pitch (MPP) is around 30~36 nm. Due to the fact that these pitches are much smaller than the resolution capability of 193 nm immersion lithography, it is also the first generation which adopts EUV photolithography technology on a large-scale where the process flow can be simplified by single exposure method from more than 10 layers. Relentless scaling brings big challenges to process integration and pushes each process module to the physical and material limit. Therefore, the success of process development will largely depend on careful balance the pros and cons to achieve both performance and yield targets. In the paper, we discussed the advantages and disadvantages of different process approaches for key process loops for 5 nm logic process flow, including dummy poly cut versus metal gate cut approaches in the metal gate loops, self-aligned contact (SAC) versus brutally aligned contact (BAC) approaches, and also introduced the self-aligned double patterning approach in the lower metal processes. Based on the above evaluation, we will provide a recommendation for module's process development.

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Section: Metal Process Approach Discussionmentioning

confidence: 99%

A Study of 2D Assist Feature Placement

Zhu¹,

Ma²,

Shen³

et al. 2019

Journal of Microelectronic Manufacturing

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“…10(a) shows an example of CD-SEM enables one to measure overlay between SiN dense line patterned by self-aligned quadrupole patterning (SAQP) process and SiO block patterned by extreme ultraviolet (EUV) exposure. 52 Edge-to-edge (EE) overlay 4 between SAQP line edge and EUV block pattern tip should be controlled. It mainly depends on line width of SAQP, length of Block pattern, and overlay between SAQP and EUV block.…”

Section: Overlay Using Edge-to-edge Overlaymentioning

confidence: 99%

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Ito

Hasumi

2019

J. Micro/Nanolith. MEMS MOEMS

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Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

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“…1 The hybrid option is to apply EUV exposure of blocks to create the tip-to-tips on the one-dimensional horizontal metal gratings achieved by ArFi-based self-aligned quadruple patterning (SAQP). 2 We can decompose these designs in generic building blocks, such as…”

Section: Introductionmentioning

confidence: 99%

Reducing extreme ultraviolet mask three-dimensional effects by alternative metal absorbers

Philipsen

Luong

Souriau

et al. 2017

J. Micro/Nanolith. MEMS MOEMS

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Over the recent years, extreme ultraviolet (EUV) lithography has demonstrated the patterning of ever-shrinking feature sizes (enabling the N7 technology node and below), whereas the EUV mask has remained unaltered, using a 70-nm tantalum (Ta)-based absorber. This has led to experimentally observed mask three-dimensional (M3D) effects at the wafer level, which are induced by the interaction between the oblique incident EUV light and the patterned absorber with typical thickness values on the order of several wavelengths. We exploit the optical properties of the absorber material of the EUV mask as an M3D mitigation strategy. Using rigorous lithographic simulations, we screen potential single-element absorber materials for their optical properties and optimal thickness for minimum best focus variation through pitch at the wafer level. In addition, the M3D mitigation by absorber material is evaluated by process window comparison of foundry N5-specific logic clips. To valid ate the rigorous simulation predictions and test the processing feasibility of the alternative absorber materials, we have selected the candidate single elements nickel and cobalt for an experimental evaluation on wafer substrates. We present the film characterization as well as the first patterning tests of these single-element candidate absorber materials

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SAQP and EUV block patterning of BEOL metal layers on IMEC's iN7 platform

Cited by 5 publications

References 2 publications

A Study of 2D Assist Feature Placement

A Study of 2D Assist Feature Placement

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Reducing extreme ultraviolet mask three-dimensional effects by alternative metal absorbers

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