Safe and efficient supervised memory systems

Bobba, Jayaram; Lupon, Marc; Hill, Mark D.; Wood, David А.

doi:10.1109/hpca.2011.5749744

Cited by 4 publications

(11 citation statements)

References 42 publications

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“…The base system model considered in Safe Supervised Memory [4] is a TSO-based system, with a supervision mechanism similar to Memtracker [17]. The Memtracker proposal itself does not make use of a write buffer.…”

Section: Correctness Issues In Tso Based Supervised Memory Systemsmentioning

confidence: 99%

“…(Correctness issues) Bobba et al [4] pointed out that retiring SMW instructions into the write buffer can causes correctness issues in the supervision scheme. It is possible that an SMR (that follows an SMW) can read its metadata before the preceding SMW in the write buffer can read its corresponding metadata.…”

Section: Correctness Issues In Tso Based Supervised Memory Systemsmentioning

confidence: 99%

“…3 The lock on A is relinquished when Wm(A) is issued to memory. 4 Now, when R m (A) is issued to memory, it locks A. Here, SMR (A) reads both its data and metadata from SMW(A), thus preserving metadata-data atomicity.…”

Section: Ensuring Atomicitymentioning

confidence: 99%

“…3 The directory responds to the request so that Rm can be retired. 4 The metadata is then processed (in P0) and the resulting metadata write is retired into the write buffer. It is worth noting that A is still in the shared state in the directory.…”

Section: Ensuring Atomicitymentioning

confidence: 99%

“…While improving performance, supervision in TSO results in certain correctness issues. Bobba et al [4] demonstrated the correctness issues in applying supervision to TSO consistency, resulting from retiring SMWs into the write buffer. An SMW that has retired into the write-buffer, performs its data and metadata op-erations only when the SMW reaches the head of the write buffer.…”

Section: Introductionmentioning

confidence: 99%

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SuperCoP

Rajaram

Nagarajan

McPherson

et al. 2012

Proceedings of the 9th Conference on Computing Frontiers

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Supervised memory systems maintain additional metadata for each memory address accessed by the program, to control and monitor accesses to the program data. Supervised systems find use in several applications including memory checking, synchronization, race detection, and transactional memory. Conventional memory instructions are replaced by supervised memory instructions (SMIs) which operate on both data and metadata atomically. Existing proposals for supervised memory systems assume sequential consistency. Recently, Bobba et al. [4] demonstrated the correctness issues (imprecise exceptions and metadata read reordering) in naively applying supervision to Total-Store-Order, and proposed two solutions -TSOall and TSOdata -for overcoming the correctness issues. TSOall solves correctness issues by forcing SMIs to perform in order, but performs similar to SC, since supervised writes cannot retire into the write-buffer. TSOdata, while allowing supervised writes to retire into the write-buffer, works correctly for only a subset of supervision schemes. In this paper we observe that correctness is ensured as long as SMIs read and process their metadata in order. We propose SuperCoP, a supervised memory system for relaxed memory models in which SMIs read and process metadata before retirement, while allowing data and metadata writes to retire into the write-buffer. Since SuperCoP separates metadata reads and their processing from the writes, we propose a simple mechanism -in the form of cache block level locking at the directory -to ensure atomicity. Our experimental results show that SuperCoP performs better than TSOall by 16.8%. SuperCoP also performs better than TSOdata by 6%, even though TSOdata is not general.

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Section: Correctness Issues In Tso Based Supervised Memory Systemsmentioning

confidence: 99%

Section: Correctness Issues In Tso Based Supervised Memory Systemsmentioning

confidence: 99%

Section: Ensuring Atomicitymentioning

confidence: 99%

Section: Ensuring Atomicitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

SuperCoP

Rajaram

Nagarajan

McPherson

et al. 2012

Proceedings of the 9th Conference on Computing Frontiers

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Design of a Dynamic Parallel Execution Architecture for Multi-core Systems

Huang

Jou

Hsieh

et al. 2013

Advances in Intelligent Systems and Applications - Volume 2

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Architectural support for high-performing hardware transactional memory systems

Lupon Navazo

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Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to this, current synchronization techniques serialize the execution of those critical sections that conflict in shared memory and thus limit the scalability of multithreaded applications. Transactional Memory (TM) has emerged as a promising programming model that solves the trade-off between high performance and ease of use. In TM, the system is in charge of scheduling transactions (atomic blocks of instructions) and guaranteeing that they are executed in isolation, which simplifies writing parallel code and, at the same time, enables high concurrency when atomic regions access different data. Among all forms of TM environments, Hardware TM (HTM) systems is the only one that offers fast execution at the cost of adding dedicated logic in the processor. Existing HTMsystems suffer considerable delays when they execute complex transactional workloads, especially when they deal with large and contending transactions because they lack adaptability. Furthermore, most HTM implementations are ad hoc and require cumbersome hardware structures to be effective, which complicates the feasibility of the design. This thesis makes several contributions in the design and analysis of low-cost HTMsystems that yield good performance for any kind of TM program. Our first contribution, FASTM, introduces a novel mechanism to elegantly manage speculative (and already validated) versions of transactional data by slightly modifying on-chip memory engine. This approach permits fast recovery when a transaction that fits in private caches is discarded. At the same time, it keeps non-speculative values in software, which allows in-place x memory updates. Thus, FASTM is not hurt from capacity issues nor slows down when it has to undo transactional modifications. Our second contribution includes two different HTM systems that integrate deferred resolution of conflicts in a conventional multicore processor, which reduces the complexity of the system with respect to previous proposals. The first one, FUSETM, combines different-mode transactions under a unified infrastructure to gracefully handle resource overflow. As a result, FUSETM brings fast transactional computation without requiring additional hardware nor extra communication at the end of speculative execution. The second one, SPECTM, introduces a two-level data versioning mechanism to resolve conflicts in a speculative fashion even in the case of overflow. Our third and last contribution presents a couple of truly flexible HTM systems that can dynamically adapt their underlying mechanisms according to the characteristics of the program. DYNTM records statistics of previously executed transactions to select the best-suited strategy each time a new instance of a transaction starts. SWAPTM takes a different approach: it tracks information of the current transactional instance to change its priority level at runtime. Both alternatives obtain great performance over existing proposals that employ fixed transactional policies, especially in applications with phase changes.

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Safe and efficient supervised memory systems

Cited by 4 publications

References 42 publications

SuperCoP

SuperCoP

Design of a Dynamic Parallel Execution Architecture for Multi-core Systems

Architectural support for high-performing hardware transactional memory systems

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