Runtime Monitoring with Recovery of the SENT Communication Protocol

Selyunin, Konstantin; Jakšić, Stefan; Nguyen, Thang; Reidl, Christian; Hafner, Udo; Bartocci, Ezio; Ničković, Dejan; Grosu, Radu

doi:10.1007/978-3-319-63387-9_17

Cited by 30 publications

(18 citation statements)

References 30 publications

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“…The clock period is fixed to 8 μs, though it may be operated at much higher frequencies. Most of the SENT designs are implemented in software, microcontrollers or FPGA [25,26]. The SENT driver presented in [27] is implemented in 180 nm CMOS process and it occupies and an area of 0.9 mm × 0.7 mm.…”

Section: Measurement and Simulation Resultsmentioning

confidence: 99%

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

Ali

Rikhan

Kim

et al. 2018

Sensors

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In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 μm × 116 μm) and 4.314 K gates. The current consumption is 50 μA from a 1.8 V supply with a total 90 μW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of −16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 μm × 680 μm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

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Section: Measurement and Simulation Resultsmentioning

confidence: 99%

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

Ali

Rikhan

Kim

et al. 2018

Sensors

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“…Recently, synthesis of hardware-based monitors from stream specifications has become an important field: For LOLA [9] constant memory bounds for an algorithm that evaluates well-formed specifications exist and for LOLA 2.0 [14] future references must be eliminated to gain constant memory bounds. There has been work on synthesis of STL to FPGAs in different ways as well [20,25].…”

Section: Time As First-class Citizenmentioning

confidence: 99%

TeSSLa: Temporal Stream-Based Specification Language

Convent

Hungerecker

Leucker

et al. 2018

Lecture Notes in Computer Science

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Runtime verification is concerned with monitoring program traces. In particular, stream runtime verification (SRV) takes the program trace as input streams and incrementally derives output streams. SRV can check logical properties and compute temporal metrics and statistics from the trace. We present TeSSLa, a temporal stream-based specification language for SRV. TeSSLa supports timestamped events natively and is hence suitable for streams that are both sparse and finegrained, which often occur in practice. We prove results on TeSSLa's expressiveness and compare different TeSSLa fragments to (timed) automata, thereby inheriting various decidability results. Finally, we present a monitor implementation and prove its correctness.

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“…There are also several approaches to execute monitors on FPGAs for various applications: synthesis for STL for observation of embedded systems is described in [14,15,24] and synthesis for past time LTL for observation of hardware buses is described in [22]. While these approaches directly synthesize FPGA designs from monitor specifications, we use processing units that are synthesized once and can be reconfigured quickly.…”

Section: Introductionmentioning

confidence: 99%

Hardware-Based Runtime Verification with Embedded Tracing Units and Stream Processing

Convent

Hungerecker

Scheffel

et al. 2018

Lecture Notes in Computer Science

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In this tutorial, we present a comprehensive approach to nonintrusive monitoring of multi-core processors. Modern multi-core processors come with trace-ports that provide a highly compressed trace of the instructions executed by the processor. We describe how these compressed traces can be used to reconstruct the actual control flow trace executed by the program running on the processor and to carry out analyses on the control flow trace in real time using FPGAs. We further give an introduction to the temporal stream-based specification language TeSSLa and show how it can be used to specify typical constraints of a cyber-physical system from the railway domain. Finally, we describe how lightweight , hardware-supported instrumentation can be used to enrich the control-flow trace with data values from the application.

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Runtime Monitoring with Recovery of the SENT Communication Protocol

Cited by 30 publications

References 30 publications

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology

TeSSLa: Temporal Stream-Based Specification Language

Hardware-Based Runtime Verification with Embedded Tracing Units and Stream Processing

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