Run-time power gating of on-chip routers using look-ahead routing

Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu; Wang, Daihan

doi:10.1109/aspdac.2008.4484015

Cited by 54 publications

(59 citation statements)

References 7 publications

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“…As opposed to this, our method pursues a minimal size hardware implementation for the power management, with fast response to changing communication load since the complete logic is implemented in hardware. In addition the centralized approach in [2] does not scale well, in contrast to our approach .Matsutani et al present run-time power gating for network routers in several publications [13], [14]. But besides a not negligible resource overhead, additional computation overhead is necessary inside the router to produce the information required to generate a wake-up request signal.…”

Section: Related Workmentioning

confidence: 93%

Noc Router With Dedicated Power Management Unit

Khanooni¹

2017

IJRASET

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Growing chip integration density and increasing frequencies lead to tremendous leakage power and henceforth to chip heat problems. Power management is one possibility to reduce the power consumption and get the temperature problem under control. Current technology mainly focuses on power-gating techniques on basis of multi-core systems but leaving the network perspective out of scope. We provide a holistic concept, bringing together voltage and frequency scaling techniques for networkon-chips. Following this, network static power consumption could be minimized without affecting the system performance. We present a light-weight power manages-ment controller for network-on-chips with online monitoring to optimize the power consumption of network resources. Our work comprises a hardware simulation model for design space exploration of varying technology specific parameters and an FPGA based prototype for verification. The power saving potent-tial heavily depend on the network communication load. Keywords-network-on-chip, router, power management, voltage scaling, frequency scaling, clock gating, power gating I.INTRODUCTION Network-on-chips (NoCs) provide a scalable communication infrastructure for architectures with huge numbers of process-ing elements. To preclude that communication becomes the bottleneck in large multiprocessor designs, powerful network routers with large throughput are necessary. Consequently the proportion of network resources of the overall resource consumption is not negligible any longer. Since the start of CPU development, processor frequency increased from few Megahertz to around three Gigahertz. However, in the last few years, core frequency growth has slowed. One of the reasons is a highly significant heat emission which comes in conjunction with increasing frequencies. Chip temperature can increase so much that it could cause actual physical damage to the chip. Because of the tremendous generated heat, simple cooling mechanisms are no longer strong enough to carry away the heat. To prevent the hardware from destruction, hardware monitors are included in the chips and switch off the device before it comes to actual damage. For taking corrective actions even before the heat increases too much, dynamic voltage and frequency scaling (DVFS) methods are applied [1]. The majority of DVFS methods focuses on the processor perspective and the communication is not considered. However, there are first developments to extend these methods also to the network layer [2], [3], [4].With shrinking technology sizes, especially beyond 90nm, the amount of static power dissipation reaches a critical proportion of the total power. Accessory, the increasing static power dissipation causes high temperatures even in idle cir-cutis and hence the static leakage is not negligible any more. The rising complexity of on-chip communication structures, is reaching a state where dedicated power management becomes beneficial. Moreover, with increasing network sizes it will not be possible to have one globally sy...

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Section: Related Workmentioning

confidence: 93%

Noc Router With Dedicated Power Management Unit

Khanooni¹

2017

IJRASET

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“…In contrast, powergating with lookahead [10,11], leads to 9-11% application slowdown if implemented at a router level, while causing as much as 20% performance loss if fine-grained power-gating is applied. Finally, Panthre leakage power savings can be as much as 36.9% on average, under the fair assumption that 10-16 nodes of a 64-node CMP are communication-idle at any given time.…”

Section: Introductionmentioning

confidence: 99%

“…However, it further worsens the problem of accumulated wakeup latencies, as it puts components to sleep more aggressively. Early wakeup with lookahead routing was proposed to compensate for wakeup latency [10]. However, for a typical 2-stage pipeline router, lookahead can only hide a small fraction of the wakeup latency, which is typically many cycles.…”

Section: Introductionmentioning

confidence: 99%

Power-Aware NoCs through Routing and Topology Reconfiguration

Parikh

Das

Bertacco

2014

Proceedings of the 51st Annual Design Automation Conference

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With the advent of multicore processors and system-on-chip designs, intra-chip communication demands have exacerbated, leading to a growing adoption of scalable networks-on-chip (NoCs) as the interconnect fabric. Today, conventional NoC designs may consume up to 30% of the entire chip's power budget, in large part due to leakage power. In this work, we address this issue by proposing Panthre: our solution deploys power-gating to provide long intervals of uninterrupted sleep to selected units. Packets that would normally use power-gated components are steered away via topology and routing reconfiguration, while Panthre provides low-latency alternate paths to their destinations. The routing reconfiguration operates in a distributed fashion and guarantees that deadlock-free routes are available at all times. At runtime, Panthre adapts to the application's communication patterns by updating its power-gating decisions. It employs a feedback-based distributed mechanism to control the amount of sleeping components and of packets detours, so that performance degradation is kept at a minimum. Our design is flexible, providing a mechanism that designers can use to tradeoff power savings with performance, based on application's requirements.Our experiments on multi-programmed communication-light workloads from the SPEC CPU2006 suite show that Panthre reduces total network power consumption by 14.5% on average, with only a 1.8% degradation in performance, when all processor nodes are active. At times when 15-25% of the processor cores are communication-idle, Panthre enables leakage power savings of 36.9% on average, while still providing connected and deadlock-free routes for all other nodes.

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“…Therefore, certain mechanism should be there for maintaining an optimum wake up latency. Various approaches have been adopted like Look ahead method [10], where the output port of a flit is calculated in advance to reduce wake up latency. Another technique called Look ahead with ever-on may be used where the first hop is always on and no wake up signal is required for that.…”

Section: Wake Up Latencymentioning

confidence: 99%

Segmented Buffer for NOC Router

Debbarma¹,

Pradhan²

2015

IJMO

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Abstract-As the number of transistors in a single chip is increasing day by day, SoC is a very popular choice among the developers as it gives more speed and functionality. The IPs in the SoCs can be from different vendors and may be used for a third party for manufacturing a chip. For effective communication among the IPs or more commonly Cores, an in built network structure called Network on Chip (NOC) has been developed over the years and different versions of NOCs are available in the present day. This paper proposes a segmented buffer structure for NOC router for effective utilization of the NOC buffers.

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Run-time power gating of on-chip routers using look-ahead routing

Cited by 54 publications

References 7 publications

Noc Router With Dedicated Power Management Unit

Noc Router With Dedicated Power Management Unit

Power-Aware NoCs through Routing and Topology Reconfiguration

Segmented Buffer for NOC Router

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