Power-Aware NoCs through Routing and Topology Reconfiguration

Abstract

With the advent of multicore processors and system-on-chip designs, intra-chip communication demands have exacerbated, leading to a growing adoption of scalable networks-on-chip (NoCs) as the interconnect fabric. Today, conventional NoC designs may consume up to 30% of the entire chip's power budget, in large part due to leakage power. In this work, we address this issue by proposing Panthre: our solution deploys power-gating to provide long intervals of uninterrupted sleep to selected units. Packets that would normally use power-gated components are steered away via topology and routing reconfiguration, while Panthre provides low-latency alternate paths to their destinations. The routing reconfiguration operates in a distributed fashion and guarantees that deadlock-free routes are available at all times. At runtime, Panthre adapts to the application's communication patterns by updating its power-gating decisions. It employs a feedback-based distributed mechanism to control the amount of sleeping components and of packets detours, so that performance degradation is kept at a minimum. Our design is flexible, providing a mechanism that designers can use to tradeoff power savings with performance, based on application's requirements.Our experiments on multi-programmed communication-light workloads from the SPEC CPU2006 suite show that Panthre reduces total network power consumption by 14.5% on average, with only a 1.8% degradation in performance, when all processor nodes are active. At times when 15-25% of the processor cores are communication-idle, Panthre enables leakage power savings of 36.9% on average, while still providing connected and deadlock-free routes for all other nodes.

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

“…Although the simpler micro-architecture allows routers to scale better and consume less power (energy), the topology of the network remains fixed, thus lightly used links cannot be excluded. Conversely, Panthre [24] integrates reconfiguration features within a conventional router micro-architecture. Despite power saving benefits, routers are based on the conventional micro-architecture.…”

Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip

“…Although the power overhead is small (especially when we compare it against the power consumption of a multi-core chip), it might create local temperature hotspots as it increases the power density as compared to a planar 2D design. To mitigate the potential thermal challenges, techniques like thermal-aware routing [1] or topology reconfiguration [7] can be used.…”

Power punch: Towards non-blocking power-gating of NoC routers

“…However, it introduces considerable packet detours and degrades system performance. More extensive but complex reconfiguration algorithms [27,28] use dynamic information to minimize detours. However, they are slow by comparison and, as a result, reconfigure only on a per-epoch basis (~10K cycles for an epoch) to capture idleness on a very coarse granularity.…”

“…NoRD also requires extra VCs for deadlock avoidance whereas Power Punch works with any number of VCs. Router Parking [28] and Panthre [27] are two other reconfiguration-based NoC power saving schemes with reasonably efficient algorithms. However, these schemes similarly suffer from issues associated with reconfiguration such as detour, long epoch and limitations on core-to-core communication.…”

“…A number of closely related works on power-gating of NoC routers have already been discussed in detail [6,7,9,24,25,26,27,28]. In addition, topology-aware powergating has also been proposed recently [31] that specifically targets Flattened bufferfly [19] and MECS [14] networks.…”