Power punch: Towards non-blocking power-gating of NoC routers

Abstract

As chip designs penetrate further into the dark silicon era, innovative techniques are much needed to power off idle or under-utilized system components while having minimal impact on performance. On-chip network routers are potentially good targets for power-gating, but packets in the network can be significantly delayed as their paths may be blocked by powered-off routers. In this paper, we propose Power Punch, a novel performance-aware, power reduction scheme that aims to achieve non-blocking power-gating of on-chip network routers. Two mechanisms are proposed that not only allow power control signals to utilize existing slack at source nodes to wake up powered-off routers along the first few hops before packets are injected, but also allow these signals to utilize hop count slack by staying ahead of packets to "punch through" any blocked routers along the imminent path of packets, preventing packets from having to suffer router wakeup latency or packet detour latency. Full system evaluation on PARSEC benchmarks shows Power Punch saves more than 83% of router static energy while having an execution time penalty of less than 0.4%, effectively achieving near non-blocking power-gating of on-chip network routers.

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

“…Power gating has been extensively explored within the context of NoCs, in order to reduce the leakage power [16,7], to improve the reliability of some part of the architecture [21,22], or both [20]. We categorize the power-gating techniques based on their operational granularity, i.e., either at the router-level (entire router switched off), or at the buffer-level (only individual buffers are switched off).…”

“…As part of BlackOut's comprehensive evaluation, this work compares the proposed methodology with two current stateof-the-art power-gating mechanisms, (1) Power Punch [7], and (2) the technique in [14]. The Power Punch mechanism [7] represents the state-of-the-art in coarse-grain power gating (i.e., powering off the entire router), while the mechanism in [14] represents the state-of-the-art in fine-grain power-gating at the buffer-level.…”

“…The Power Punch mechanism [7] represents the state-of-the-art in coarse-grain power gating (i.e., powering off the entire router), while the mechanism in [14] represents the state-of-the-art in fine-grain power-gating at the buffer-level. The experimental results -obtained using both synthetic traffic and real applications -demonstrate that BlackOut substantially outperforms both existing state-of-theart techniques.…”

“…The Power Punch [7] methodology promises non-blocking power gating in NoC routers. It tries to completely hide the router's wake-up latency of 8 cycles by sending wake-up signals up to 3 hops in advance, adding the capability of hiding a variable number of cycles depending on the router's pipeline.…”

“…The design of effective power-gating methodologies for NoCs -aiming to aggressively reduce leakage power consumption -is usually achieved by means of complex and customdesigned mechanisms. Such architectures exploit additional gather networks to steer information to a centralized power-gating module [8], or they implement complex forwarding networks to timely provide prevailing traffic information to distributed powergating modules [7].…”