Rule-Based Design for Multiple Nodes Upset Tolerant Latch Architecture

Sajjade, Faisal Mustafa; Goyal, Neeraj Kumar; Varaprasad, B.K.S.V.L.

doi:10.1109/tdmr.2019.2945917

Cited by 16 publications

(7 citation statements)

References 28 publications

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“…In this section, a review of self-recoverable DNU and DNU tolerant D-latches is presented. Previous hardened latch designs such as double-node charge sharing (DNCS) SEU tolerant latch [7], non-temporally hardened latch (NTHLTCH) [10], triple path dual-interlocked storage cell (TPDICE)-based latch [18], LSEDUT latch [12], DNU self-recoverable latch design for high performance and low power application (DNURHL) latch [19], and rule-based DNU tolerant latch (RDTL) [17] are analyzed.…”

Section: State Of the Art: Previous Hardened Latch Designsmentioning

confidence: 99%

“…The DNURHL D-latch is not self-recoverable since the node pairs of C-element inputs are repeated, and these input pairs suffer from improper feedback to the output nodes of these Celements. This problem is solved in RDTL (figure 1(f)), which is designed based on rule design so that the pairs of nodes of input C-elements are not repeated, presenting appropriate feedback in loops to become fully self-recoverable against DNU [17]. However, the RDTL, in comparison with the DNURHL latch, has more transmission gates and inverters, which introduces more area and power consumption penalty.…”

Section: F Rdtl Latchmentioning

confidence: 99%

“…This paper presents a novel and improved low-cost DNUself-recoverable D-latch to meet the demand for reliable and low-cost circuits for harsh environments. This proposed Dlatch is an improvement of the low-cost single-event doublenode upset tolerant (LSEDUT) latch [12] based on the rule design for multiple nodes upset tolerant latch architecture [17], to confer it with self-recoverability. By using a different design approach, such as a clock-gating (CG) technique, this proposed D-latch has a lower transistor count, which results in lower power and area consumption.…”

Section: Introductionmentioning

confidence: 99%

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Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

et al. 2023

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This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost profile. Thus, this D-latch may be useful for high reliability and high-performance safety-critical applications as it can detect and recover faults happening during holding time in harsh radiation environments. The proposed D-latch design is based on a low-cost single event double-node upset tolerant latch and a rule-based double-node upset (DNU) tolerant latch which provides it with the self-recoverability against DNU, but paired with a low transistor count and high performance. Simulation waveforms support the achievements and demonstrate that this new D-latch is fully self-recoverable against double-node upset. In addition, the minimum improvement of the delay-power-area product of the proposed rule-based design for the low-cost DNU tolerant self-recoverable latch (RB-LDNUR) is 59%, compared with the latest DNU self-recoverable latch on the literature.INDEX TERMS Delay-power-area product (DPAP), Double node upsets (DNU), High impedance state (HIS), Low cost single event double node upset tolerant (LSEDUT), Power-delay product (PDP), Single node upset (SNU), Soft error (SE).

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Section: State Of the Art: Previous Hardened Latch Designsmentioning

confidence: 99%

Section: F Rdtl Latchmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

et al. 2023

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“…Later in time, some of DNU hardened D-latches [15] have been proposed to face this issue, nonetheless, in their designs there is one-pair of their nodes that cannot tolerate high charges, which means they are not completely DNUs self-recoverable. One step beyond is given in [5], [16]- [18], where DNU D-latches able to fully self-recover are presented, however, those designs are lacking the triplenode-upset (TNU) tolerance. This latter challenge has been addressed in [8], [19] where TNU can be tolerated but not self-recovered.…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

et al. 2022

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As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU) tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features; in particular, this approach enhances its reliability against process variations, such as threshold voltage and (W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch: it can mask single event transients. Specific figures of merit endorse the gains introduced by the new design: compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8% and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch.INDEX TERMS Power-delay product (PDP), soft errors (SE), single event upset (SEU), high impedance state (HIS), single event transient (SET), dual interlocked storage cell (DICE), triple path DICE (TPDICE), quadruple-node upsets (QNUs).

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“…Devices dimensions are increasingly descending as the technology node scaling, which renders static random access memories (SRAMs) extensively applied in aerospace are more sensitive to single event upsets (SEUs) induced by radiation particles [1,2,3,4,5,6,7]. SEUs caused by a reversed-bias p-n junction collecting excessive charge on which energetic particles striking give rise to data upset, namely, destroy the data integrity and then conduce to function failure of logic elements, such as latch [8,9,10,11,12,13], DFF, SRAM bit-cell. Among these digital modules, we focus on the memory cell occupying a large portion of total memories area.…”

Section: Introductionmentioning

confidence: 99%