Row-buffer decoupling: A case for low-latency DRAM microarchitecture

Seongil, O; Son, Young Hoon; Kim, Nam Sung; Ahn, Jung Ho

doi:10.1109/isca.2014.6853230

Cited by 15 publications

(8 citation statements)

References 22 publications

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“…Manuscript received: 2019-12-09; accepted: 2019- [12][13][14][15][16][17][18][19] With the scaling of data centers and web services, applications are becoming increasingly memory hungry, which makes the memory system have a significant impact on the overall performance and energy efficiency of the data centers. Due to the advancement of memory technologies, DRAM capacity and bandwidth have been dramatically improved across generations during the past decades [1,2] . However, memory latency remains almost constant across generations [3] , exacerbating the performance gap between the memory system and the processor, which is known as the "memory wall" problem.…”

Section: Introductionmentioning

confidence: 99%

“…Extensive recent researches have been conducted on mitigating the "memory wall" problem via reducing memory latency. Various factors can affect the memory latencies, such as DRAM refresh [4][5][6][7] , row buffer overfetch [2,8] , and interference between competing processes [9] . In fact, the increase in memory capacity can hurt memory latency [3] .…”

Section: Introductionmentioning

confidence: 99%

“…In fact, the increase in memory capacity can hurt memory latency [3] . The primary reason is that the bitlines connected to the row buffer become longer as capacity grows, which leads to dramatically increased associated parasitic capacitance, and thus increases DRAM access latency [2,3] . This paper focuses on reducing the latencies caused by row buffer overfetch [10,11] , which is one of the most performance and energy inefficient DRAM operations in modern multi-core systems.…”

Section: Introductionmentioning

confidence: 99%

“…To improve the row buffer utilization, various approaches have been proposed. Some works suggest to maximize the utilization of the row buffer by scheduling [2] , or group the memory requests by the targeting rows at the memory controller [8] . Other works try to mitigate the latencies by taking advantage of DRAM characteristics that accessing the rows near the row buffer incurs less latencies [3] .…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

RBC: A memory architecture for improved performance and energy efficiency

Liu

Zhou

Huang

et al. 2021

Tinshhua Sci. Technol.

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DRAM-based memory suffers from increasing row buffer conflicts, which causes significant performance degradation and power consumption. As memory capacity increases, the overheads of the row buffer conflict are increasingly worse as increasing bitline length, which results in high row activation and precharge latencies. In this work, we propose a practical approach called Row Buffer Cache (RBC) to mitigate row buffer conflict overheads efficiently. At the core of our proposed RBC architecture, the rows with good spatial locality are cached and protected, which are exempted from being interrupted by the accesses for rows with poor locality. Such an RBC architecture significantly reduces the overheads of performance and energy caused by row activation and precharge, and thus improves overall system performance and energy efficiency. We evaluate RBC architecture using SPEC CPU2006 on a DDR4 memory compared to a commodity baseline memory system. Results show that RBC improves the overall performance by up to 2:24 (16:1% on average) and reduces the memory energy by up to 68:2% (23:6% on average) for single-core simulations. For multi-core simulations, RBC increases the overall performance by up to 1:55 (17% on average) and reduces memory energy consumption by up to 35:4% (21:3% on average).

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

RBC: A memory architecture for improved performance and energy efficiency

Liu

Zhou

Huang

et al. 2021

Tinshhua Sci. Technol.

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“…To address the aforesaid issues in shared memory systems, several techniques have been proposed for main memory optimisation. They are hardware and software-based cache bypassing techniques [3][4][5][6][7], cache insertion and replacement policies [8], memory scheduling for CPU and GPU [4,[9][10][11], DRAM design [12][13][14][15][16][17][18][19], hardware accelerator [20][21][22][23][24][25][26][27], Processing-in-Memory (PIM) [28][29][30][31][32][33][34][35][36], etc.…”

Section: Introductionmentioning

confidence: 99%

Survey on memory management techniques in heterogeneous computing systems

Hazarika

Poddar

Rahaman

2020

IET Computers & Digital Techniques

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A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory-centric hardware accelerator in the heterogeneous system and Processing-in-Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self-adaptive memory management schemes in the high-speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.

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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

Oliveira¹,

Gómez-Luna

Orosa

et al. 2021

IEEE Access

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Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ a range of techniques to reduce overheads tied to data movement, spanning from traditional mechanisms (e.g., deep multi-level cache hierarchies, aggressive hardware prefetchers) to emerging techniques such as Near-Data Processing (NDP), where some computation is moved close to memory. Prior NDP works investigate the root causes of data movement bottlenecks using different profiling methodologies and tools. However, there is still a lack of understanding about the key metrics that can identify different data movement bottlenecks and their relation to traditional and emerging data movement mitigation mechanisms. Our goal is to methodically identify potential sources of data movement over a broad set of applications and to comprehensively compare traditional compute-centric data movement mitigation techniques (e.g., caching and prefetching) to more memory-centric techniques (e.g., NDP), thereby developing a rigorous understanding of the best techniques to mitigate each source of data movement. With this goal in mind, we perform the first large-scale characterization of a wide variety of applications, across a wide range of application domains, to identify fundamental program properties that lead to data movement to/from main memory. We develop the first systematic methodology to classify applications based on the sources contributing to data movement bottlenecks. From our large-scale characterization of 77K functions across 345 applications, we select 144 functions to form the first open-source benchmark suite (DAMOV) for main memory data movement studies. We select a diverse range of functions that (1) represent different types of data movement bottlenecks, and (2) come from a wide range of application domains. Using NDP as a case study, we identify new insights about the different data movement bottlenecks and use these insights to determine the most suitable data movement mitigation mechanism for a particular application. We open-source DAMOV and the complete source code for our new characterization methodology at https: //github.com/CMU-SAFARI/DAMOV.

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Row-buffer decoupling: A case for low-latency DRAM microarchitecture

Cited by 15 publications

References 22 publications

RBC: A memory architecture for improved performance and energy efficiency

RBC: A memory architecture for improved performance and energy efficiency

Survey on memory management techniques in heterogeneous computing systems

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

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