RBC: A memory architecture for improved performance and energy efficiency

Abstract

DRAM-based memory suffers from increasing row buffer conflicts, which causes significant performance degradation and power consumption. As memory capacity increases, the overheads of the row buffer conflict are increasingly worse as increasing bitline length, which results in high row activation and precharge latencies. In this work, we propose a practical approach called Row Buffer Cache (RBC) to mitigate row buffer conflict overheads efficiently. At the core of our proposed RBC architecture, the rows with good spatial locality are cached and protected, which are exempted from being interrupted by the accesses for rows with poor locality. Such an RBC architecture significantly reduces the overheads of performance and energy caused by row activation and precharge, and thus improves overall system performance and energy efficiency. We evaluate RBC architecture using SPEC CPU2006 on a DDR4 memory compared to a commodity baseline memory system. Results show that RBC improves the overall performance by up to 2:24 (16:1% on average) and reduces the memory energy by up to 68:2% (23:6% on average) for single-core simulations. For multi-core simulations, RBC increases the overall performance by up to 1:55 (17% on average) and reduces memory energy consumption by up to 35:4% (21:3% on average).

Metallization system as a part of thermal memory

“…Generally, DRAM is one of the main elements of a modern computer [ 1 ]. After the start-up, active programs and data used during the entire session are stored in memory.…”

“…As a rule, memory elements (1T-1C DRAM) are based on metal-oxide-semiconductor field-effect transistor [ 1 , 3 ]. Currently, they widely use single-transistor structures, which have a connector to the bit line in addition to the 1T-1C DRAM memory element [ 4 ].…”

LLAMA: The low‐level abstraction for memory access

“…Moreover, the increasing heterogeneity of computing hardware means that optimal access patterns vary between platforms and portable efficient data transport becomes a challenge. We observe a proliferation of specialized compute and memory hardware architectures to fight the increasing gap between compute and memory capabilities, including Google's tensor processing units (TPUs), 4 the PEZY SC many-core microprocessors, 5 Fujitsu's A64FX processor powering the Fugaku supercomputer, 6 near-memory 7 and in-memory 8 computing architectures, DRAM modules with additional SRAM caches for their row buffers, 9 and others. 10 Modern hardware is only used efficiently if its internal structure is respected.…”